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PMIC Layout Guidelines

2013-09-22
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Introduction When using a high-frequency switching regulator such as the MAX16922, a good PCB layout will provide a clean output supply and save considerable time in the EMI chamber debugging emissions issues. This application note outlines some critical areas of the circuit where optimizing the layout provides the most benefit. General layout guidelines 1. For OUT1: minimize the trace loop area for the input capacitors (C3 and C5), inductor (L1), catch diode (D1), and output capacitor (C12). 2. For OUT2: minimize the trace loop area for the input capacitor (C10), inductor (L2), and output capacitor (C11). 3. Connect the power ground (pin 9 and anode of D1) to the rest of the grounds at one point near the exposed pad under the MAX16922. This connection will minimize the noise coupling into the device\'s error amplifiers. 4. A shorter trace is better than a wider trace.

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