rar

Design of sequential circuit test sequence based on binary tree

  • 2013-09-22
  • 526.21KB
  • Points it Requires : 2

  In order to realize the state verification and fault detection of sequential circuits, an input test sequence needs to be designed in advance. Based on the characteristics of binary tree nodes and branches, a binary tree of sequential circuit states is established. According to the hierarchical logical relationship between circuit binary tree nodes (states) and branches (inputs), a sequential circuit test sequence can be designed intuitively and conveniently. By stimulating the circuit to be tested with a test sequence, it can be verified whether the circuit has all the predetermined states and whether the predetermined state transition can be achieved.

unfold

You Might Like

Uploader
froglucky
 

Recommended ContentMore

Popular Components

Just Take a LookMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

About Us Customer Service Contact Information Datasheet Sitemap LatestNews


Room 1530, 15th Floor, Building B, No.18 Zhongguancun Street, Haidian District, Beijing, Postal Code: 100190 China Telephone: 008610 8235 0740

Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号
×