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The Design of a Clock Synchronization Sub system for Parallel Embedded Systems

  • 2013-09-20
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Software tools are being developed to support a design methodology specic to parallelrealtime continuousdataow embedded systems This paper describes the design of aglobal clock subsystem which is an essential component of an event trace tool A newamalgam of algorithms is proposed which attends to the tradeo between clock accuracyand the need to restrict disturbance of the application whilst recording traces The detailsof an implementation on a hybrid parallel processor as well as the results of tracingapplications in the given problem domain are included

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