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Parallel port with open drain output

  • 2014-03-05
  • 2.29KB
  • Points it Requires : 1

Implement open-drain output parallel port, support 3.3V or 5V, support FPGA PS configuration function. 8-bit configuration data automatically shifts output, input clock 24MHz, generates 1MHz configuration clock. 8-bit CPU data bus interface, 11-bit address bus. Support IO set clear function.

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