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irf630 chip parameter information PDF

2013-09-20
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Summary of IRF630 design parameters (1) n/n+ epitaxial wafer, crystal orientation (100), substrate resistivity 0.004Ω cm (arsenic doped), silicon wafer thickness 450 μm, epitaxial layer resistivity 3.4-3.8Ω cm, epitaxial layer thickness 19-21μm (phosphorus implantation process). (Note: During the process, the substrate back-diffusion to the epitaxial layer is about 1.6 μm) (2) Vertical structural parameters: I. P+ diffusion junction depth 3.3 μm, concentration 8×1018-3.5×1019. II. P- diffusion junction depth 2.4μm, concentration 2.830×1017. III. N+ diffusion junction depth 0.4 μm. Concentration ﹥5×1020. IV. Gate oxide layer thickness 5000A. V. Al film thickness greater than 2μm. (3) Horizontal structural parameters: I. Square unit cell, square arrangement. The size of the polysilicon cell is 9μm, the size of the diffusion window area is 8μm, II. The area of the cell is 17μm×17μm = 289μm². III. The chip area is 2434μm×2417μm=5.88mm². IV. The gate pad area is 247μm×187µm=0.0462mm². V. The total number of effective cells in the device is 17118. VI. The effective area of the device is 17118×289μm²=4.95mm². VII. The scribe line is 66μm horizontally and 63μm vertically. VIII. The total area is 2.5×2.48＝6.2mm². (4) Design rules: Overlay accuracy: 1.5 microns; minimum size: 2 microns

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