Temperature ranges as follows: A Version: –40°C to +85°C.
2
The AD7470 functionally works at 2.35 V. Typical specifications @ 25°C for SNR (100 kHz) = 59 dB; THD (100 kHz) = –84 dB; INL
±
0.8 LSB.
3
The AD7470 will typically maintain A-grade performance up to 125°C, with a reduced CLK of 20 MHz @ 5 V and 16 MHz @ 3 V. Typical sleep mode current @ 125°C is 700 nA.
4
Sample tested @ 25°C to ensure compliance.
5
See Power vs. Throughput Rate section.
Specifications subject to change without notice.
–2–
REV. B
AD7470/AD7472
=
2.5 V, and B Versions:
AD7472–SPECIFICATIONS
1
(V MHz2.7 V3 to 5.25 TV , REFTIN =unless Aotherwise noted.) f
20
@ V, T =
to
,
DD
2
A
MIN
MAX
CLKIN
= 26 MHz @ 5 V and
Parameter
A Version
1
3V
69
68
70
68
–78
–84
–75
–81
–86
–76
–77
–86
–77
–86
5
15
20
12
±
2
±
1.8
±
10
±
2
5V
69
68
70
68
–83
–83
–75
–86
–86
–76
–77
–86
–77
–86
5
15
20
12
±
1
B Version
1
3V
69
68
70
68
–78
–84
–75
–81
–86
–76
–77
–86
–77
–86
5
15
20
12
±
1
±
0.9
±
10
±
2
Unit
dB typ
dB min
dB typ
dB min
dB typ
dB typ
dB max
dB typ
dB typ
dB max
dB typ
dB typ
dB typ
dB typ
ns typ
ps typ
MHz typ
Bits
LSB max
LSB max
LSB max
LSB max
V
µA
max
pF typ
V
µA
max
pF typ
V min
V max
µA
max
pF max
V min
V max
µA
max
pF max
Test Conditions/Comments
f
S
= 1.5 MSPS @ 5 V, f
S
= 1.2 MSPS @ 3 V
f
IN
= 500 kHz Sine Wave
f
IN
= 100 kHz Sine Wave
f
IN
= 500 kHz Sine Wave
f
IN
= 100 kHz Sine Wave
f
IN
= 500 kHz Sine Wave
f
IN
= 100 kHz Sine Wave
f
IN
= 100 kHz Sine Wave
f
IN
= 500 kHz Sine Wave
f
IN
= 100 kHz Sine Wave
f
IN
= 100 kHz Sine Wave
f
IN
= 500 kHz Sine Wave
f
IN
= 100 kHz Sine Wave
f
IN
= 500 kHz Sine Wave
f
IN
= 100 kHz Sine Wave
@ 3 dB
f
S
= 1.5 MSPS @ 5 V
,
f
S
= 1.2 MSPS @ 3 V
DYNAMIC PERFORMANCE
5V
Signal to Noise + Distortion (SINAD) 69
68
Signal-to-Noise Ratio (SNR)
70
68
Total Harmonic Distortion (THD) –83
–83
–75
Peak Harmonic or Spurious Noise
(SFDR)
–86
–86
–76
Intermodulation Distortion (IMD)
Second-Order Terms
–77
–86
Third-Order Terms
–77
–86
Aperture Delay
5
Aperture Jitter
15
Full Power Bandwidth
20
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
REFERENCE INPUT
REF IN Input Voltage Range
DC Leakage Current
Input Capacitance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN3
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
V
DD
I
DD4
Normal Mode
Quiescent Current
Normal Mode
Quiescent Current
Sleep Mode
Power Dissipation
4
Normal Mode
Sleep Mode
12
±
2
±
1.8
±
10
±
2
±
0.9
±
10
±
2
Guaranteed No Missed Codes to 11 Bits
(A Version)
Guaranteed No Missed Codes to 12 Bits
(B Version)
0 to REF IN 0 to REF IN
±
1
±
1
33
33
2.5
±
1
10/20
2.4
0.4
±
1
10
2.5
±
1
10/20
2.4
0.4
±
1
10
0 to REF IN 0 to REF IN
±
1
±
1
33
33
2.5
±
1
10/20
2.4
0.4
±
1
10
2.5
±
1
10/20
2.4
0.4
±
1
10
±
1% for Specified Performance
Track-and-Hold Mode
Typically 10 nA, V
IN
= 0 V or V
DD
I
SOURCE
= 200
µA
I
SINK
= 200
µA
V
DD
= 2.7 V to 5.25 V
V
DRIVE
– 0.2 V
DRIVE
– 0.2
0.4
0.4
±
10
±
10
10
10
Straight (Natural) Binary
14
135
1.5
+2.7/+5.25
2.4
900
1.5
800
1
12
4.5
5
3
14
135
1.2
V
DRIVE
– 0.2 V
DRIVE
– 0.2
0.4
0.4
±
10
±
10
10
10
Straight (Natural) Binary
14
135
1.5
+2.7/+5.25
2.4
900
1.5
800
1
12
4.5
5
3
14
135
1.2
CLK IN
Cycles (max)
ns min
MSPS max
V min/max
mA max
µA
max
mA max
µA
max
µA
max
mW max
mW max
µW
max
µW
max
Conversion Time + Acquisition Time
Digital Inputs = 0 V or DV
DD
V
DD
= 4.75 V to 5.25 V; Typ 2 mA; f
S
= 1.5 MSPS
V
DD
= 4.75 V to 5.25 V; f
S
= 1.5 MSPS
V
DD
= 2.7 V to 3.3 V; Typ 1.3 mA; f
S
= 1.2 MSPS
V
DD
= 2.7 V to 3.3 V; f
S
= 1.2 MSPS
CLK IN = 0 V or DV
DD
Digital Inputs = 0 V or DV
DD
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 5 V; CLK IN = 0 V or DV
DD
V
DD
= 3 V; CLK IN = 0 V or DV
DD
NOTES
1
Temperature ranges as follows: A and B Versions: –40°C to +85°C.
2
The AD7472 functionally works at 2.35 V. Typical specifications @ 25°C for SNR (100 kHz) = 68 dB; THD (100 kHz) = –84 dB; INL
±
0.8 LSB.
3
Sample tested @ 25°C to ensure compliance.
4
See Power vs. Throughput Rate section.
Specifications subject to change without notice.
REV. B
–3–
AD7470/AD7472
AD7472–SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
Signal to Noise + Distortion (SINAD)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
REFERENCE INPUT
REF IN Input Voltage Range
DC Leakage Current
Input Capacitance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN3
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
V
DD
I
DD4
Normal Mode
Quiescent Current
Normal Mode
Quiescent Current
Sleep Mode
Power Dissipation
4
Normal Mode
Sleep Mode
5V
69
68
70
68
–83
–83
–75
–86
–86
–76
–77
–86
–77
–86
5
15
20
12
±
2
±
1.8
±
10
±
2
=
V
2.5 V,Y Version:
CLKIN
=
1
(V
DD
MHz2.7 V to 5.25 T , REFTIN =unless otherwise fnoted.) 20 MHz @ 5 V and
14
@ 3 V; T =
to
,
A
MIN
MAX
2
Y Version
1
3V
69
68
70
68
–78
–84
–75
–81
–86
–76
–77
–86
–77
–86
5
15
20
12
±
2
±
1.8
±
10
±
2
0 to REF IN
±
1
33
2.5
±
1
10/20
2.4
0.4
±
1
10
Unit
dB typ
dB min
dB typ
dB min
dB typ
dB typ
dB max
dB typ
dB typ
dB max
dB typ
dB typ
dB typ
dB typ
ns typ
ps typ
MHz typ
Bits
LSB max
LSB max
LSB max
LSB max
V
µA
max
pF typ
V
µA
max
pF typ
V min
V max
µA
max
pF max
V min
V max
µA
max
pF max
Test Conditions/Comments
f
S
= 1.2 MSPS @ 5 V, f
S
= 875 kSPS @ 3 V
f
IN
= 500 kHz Sine Wave
f
IN
= 100 kHz Sine Wave
f
IN
= 500 kHz Sine Wave
f
IN
= 100 kHz Sine Wave
f
IN
= 500 kHz Sine Wave
f
IN
= 100 kHz Sine Wave
f
IN
= 100 kHz Sine Wave
f
IN
= 500 kHz Sine Wave
f
IN
= 100 kHz Sine Wave
f
IN
= 100 kHz Sine Wave
f
IN
= 500 kHz Sine Wave
f
IN
= 100 kHz Sine Wave
f
IN
= 500 kHz Sine Wave
f
IN
= 100 kHz Sine Wave
@ 3 dB
f
S
= 1.2 MSPS @ 5 V; f
S
= 875 kSPS @ 3 V
Guaranteed No Missed Codes to 11 Bits
0 to REF IN
±
1
33
2.5
±
1
10/20
2.4
0.4
±
1
10
±
1% for Specified Performance
Track-and-Hold Mode
Typically 10 nA, V
IN
= 0 V or V
DD
I
SOURCE
= 200
µA
I
SINK
= 200
µA
V
DD
= 2.7 V to 5.25 V
V
DRIVE
– 0.2
V
DRIVE
– 0.2
0.4
0.4
±
10
±
10
10
10
Straight (Natural) Binary
14
140
1200
+2.7/+5.25
2.4
900
1.5
800
2
12
4.5
10
6
14
140
875
CLK IN Cycles (max)
ns min
kSPS max
V min/max
mA max
µA
max
mA max
µA
max
µA
max
mW max
mW max
µW
max
µW
max
Conversion Time + Acquisition Time
Digital Inputs = 0 V or DV
DD
V
DD
= 4.75 V to 5.25 V; f
S
= 1.2 MSPS; Typ 2 mA
V
DD
= 4.75 V to 5.25 V; f
S
= 1.2 MSPS
V
DD
= 2.7 V to 3.3 V; f
S
= 875 kSPS; Typ 1.3 mA
V
DD
= 2.7 V to 3.3 V; f
S
= 875 kSPS
CLK IN = 0 V or DV
DD
Digital Inputs = 0 V or DV
DD
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 5 V; CLK IN = 0 V or DV
DD
V
DD
= 3 V; CLK IN = 0 V or DV
DD
NOTES
1
Temperature ranges as follows: Y Version: –40°C to +125°C.
2
The AD7472 functionally works at 2.35 V. Typical specifications @ 25°C for SNR (100 kHz) = 68 dB; THD (100 kHz) = –84 dB; INL
±
0.8 LSB.
3
Sample tested @ 25°C to ensure compliance.
4
See Power vs. Throughput Rate section.
Specifications subject to change without notice.
–4–
REV. B
AD7470/AD7472
TIMING SPECIFICATIONS
1
(V
Parameter
f
CLK 2
t
CONVERT
t
WAKEUP
t
1
t
2
10
30
436.42
1
10
10
30
t
3
t
4 3
t
5
t
6 3
t
7 4
t
8
t
9
t
10
0
0
20
15
8
0
135
100
DD
= 2.7 V to 5.25 V, REF IN = 2.5 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Unit
kHz min
MHz max
ns min
µs
max
ns min
ns max
ns max
ns max
ns max
ns max
ns max
ns min
ns min
ns max
ns max
ns max
ns max
ns min
Description
Limit at T
MIN
, T
MAX
AD7470
AD7472
10
26
531.66
1
10
10
15
30
35
0
0
20
15
8
0
135
140
100
t
CLK
= 1/f
CLK IN
Wake-Up Time
CONVST
Pulse Width
CONVST
to BUSY Delay,
V
DD
= 5 V, A and B Versions
V
DD
= 5 V, Y Version
V
DD
= 3 V, A and B Versions
V
DD
= 3 V, Y Version
BUSY to
CS
Setup Time
CS
to
RD
Setup Time
RD
Pulse Width
Data Access Time After Falling Edge of
RD
Bus Relinquish Time After Rising Edge of
RD
CS
to
RD
Hold Time
Acquisition Time
A and B Versions
Y Version
Quiet Time
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
See Figure 1.
2
Mark/Space ratio for the CLK inputs is 40/60 to 60/40. First CLK pulse should be 10 ns min from falling edge of
CONVST.
3
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4
t
7
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
7
, quoted in the timing characteristics, is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
200 A
I
OL
TO OUTPUT
PIN
1.6V
C
L
50pF
200 A
I
OH
Figure 1. Load Circuit for Digital Output Timing Specifications