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FDC642P Single P-Channel 2.5V Specified PowerTrench
®
MOSFET
January 2010
FDC642P
Single P-Channel 2.5V Specified PowerTrench
®
MOSFET
-20 V, -4.0 A, 65 mΩ
Features
Max r
DS(on)
= 65 mΩ at V
GS
= -4.5 V, I
D
= -4.0 A
Max r
DS(on)
= 100 mΩ at V
GS
= -2.5 V, I
D
= -3.2 A
Fast switching speed
Low gate charge (11nC typical)
High performance trench technology for extremely low r
DS(on)
SuperSOT
TM
-6 package: small footprint (72% smaller than
standard SO-8); low profile (1 mm thick)
Termination is Lead-free and RoHS Compliant
General Description
This P-Channel 2.5V specified MOSFET is produced using
Fairchild’s advanced PowerTrench
®
process that has been
especially tailored to minimize on-state resistance and yet
maintain low gate charge for superior switching performance.
These devices have been designed to offer exceptional power
dissipation in a very small footprint for applications where the
FDC642P Single P-Channel 2.5V Specified PowerTrench
®
MOSFET
Electrical Characteristics
T
J
= 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV
DSS
∆BV
DSS
∆T
J
I
DSS
I
GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I
D
= -250
µA,
V
GS
= 0 V
I
D
= -250
µA,
referenced to 25°C
V
DS
= -16 V, V
GS
= 0 V
V
GS
= ±8 V, V
DS
= 0 V
-20
-13
-1
±10
V
mV/°C
µA
µA
On Characteristics
V
GS(th)
∆V
GS(th)
∆T
J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V
GS
= V
DS
, I
D
= -250
µA
I
D
= -250
µA,
referenced to 25°C
V
GS
= -4.5 V, I
D
= -4.0 A
r
DS(on)
Static Drain to Source On Resistance
V
GS
= -2.5 V, I
D
= -3.2 A
V
GS
= -4.5 V, I
D
= -4.0 A,
T
J
= 125°C
V
DS
= -5 V, I
D
= -4.0 A
-0.4
-0.6
2.5
45
55
62
15
65
100
90
S
mΩ
-1.5
V
mV/°C
g
FS
Forward Transconductance
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V
DS
= -10 V, V
GS
= 0 V,
f = 1 MHz
700
110
95
925
150
145
pF
pF
pF
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
V
DD
= -10 V, I
D
= -4 A
V
GS
= --4.5 V
V
DD
= -10 V, I
D
= -1 A,
V
GS
= -4.5 V, R
GEN
= 6
Ω
6
7
120
52
11
1.1
3.0
12
14
190
83
16
ns
ns
ns
ns
nC
nC
nC
Drain-Source Diode Characteristics
I
S
V
SD
Maximum Continuous Drain-Source Diode Forward Current
Source-Drain Diode Forward Voltage
V
GS
= 0 V, I
S
= -1.3 A
(Note 2)
-0.7
-1.3
-1.2
A
V
Notes:
1: R
θJA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
R
θJC
is guaranteed by design while R
θCA
is determined by the user’s board design.
a. 78
°C/W when mounted on a 1 in
2
pad of 2 oz copper.
b. 156
°C/W when mounted on a minimum pad of 2 oz copper.
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