CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
36-Mbit QDR
®
II SRAM Two-Word
Burst Architecture
36-Mbit QDR
®
II SRAM Two-Word Burst Architecture
Features
■
Configurations
CY7C1425KV18 – 4M × 9
CY7C1412KV18 – 2M × 18
CY7C1414KV18 – 1M × 36
Separate independent read and write data ports
❐
Supports concurrent transactions
333 MHz clock for high bandwidth
Two-word burst on all accesses
Double data rate (DDR) Interfaces on both read and write ports
(data transferred at 666 MHz) at 333 MHz
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Single multiplexed address input bus latches address inputs
for both read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
QDR
®
II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
Operates similar to QDR I device with 1 cycle read latency when
DOFF is asserted LOW
Available in × 9, × 18, and × 36 configurations
Full data coherency, providing most current data
Core V
DD
= 1.8 V (±0.1 V); I/O V
DDQ
= 1.4 V to V
DD
❐
Supports both 1.5 V and 1.8 V I/O supply
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
Offered in both Pb-free and non Pb-free Packages
Variable drive HSTL output buffers
JTAG 1149.1 compatible test access port
Phase locked loop (PLL) for accurate data placement
■
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Functional Description
The CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18
are 1.8 V synchronous pipelined SRAMs, equipped with QDR II
architecture. QDR II architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II architecture has separate data inputs and
data outputs to completely eliminate the need to “turnaround” the
data bus that exists with common I/O devices. Access to each
port is through a common address bus. Addresses for read and
write addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the QDR II read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with two 9-bit
words (CY7C1425KV18), 18-bit words (CY7C1412KV18), or
36-bit words (CY7C1414KV18) that burst sequentially into or out
of the device. Because data can be transferred into and out of
the device on every rising edge of both input clocks (K and K and
C and C), memory bandwidth is maximized while simplifying
system design by eliminating bus turnarounds.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
For a complete list of related documentation, click
here.
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Selection Guide
Description
Maximum operating frequency
Maximum operating current
×9
× 18
× 36
333 MHz
333
730
750
910
300 MHz
300
680
700
850
250 MHz
250
590
610
730
Unit
MHz
mA
Cypress Semiconductor Corporation
Document Number: 001-57825 Rev. *N
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 16, 2016
CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
Logic Block Diagram – CY7C1425KV18
D
[8:0]
9
Read Add. Decode
Write Add. Decode
A
(20:0)
21
Write
Reg
Address
Register
Write
Reg
Address
Register
21
A
(20:0)
2M x 9 Array
2M x 9 Array
K
K
CLK
Gen.
Control
Logic
RPS
C
C
CQ
DOFF
Read Data Reg.
18
V
REF
WPS
BWS
[0]
9
Control
Logic
9
Reg.
Reg.
Reg.
9
9
9
CQ
Q
[8:0]
Logic Block Diagram – CY7C1412KV18
D
[17:0]
18
Read Add. Decode
Write Add. Decode
A
(19:0)
20
Write
Reg
Address
Register
Write
Reg
Address
Register
20
A
(19:0)
1M x 18 Array
1M x 18 Array
K
K
CLK
Gen.
Control
Logic
RPS
C
C
CQ
DOFF
Read Data Reg.
36
V
REF
WPS
BWS
[1:0]
18
Control
Logic
18
Reg.
Reg.
Reg. 18
18
18
CQ
Q
[17:0]
Document Number: 001-57825 Rev. *N
Page 2 of 33
CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
Logic Block Diagram – CY7C1414KV18
36
D
[35:0]
Read Add. Decode
Write Add. Decode
A
(18:0)
19
Write
Reg
Address
Register
Write
Reg
Address
Register
19
A
(18:0)
512K x 36 Array
512K x 36 Array
K
K
CLK
Gen.
Control
Logic
RPS
C
C
CQ
DOFF
Read Data Reg.
72
V
REF
WPS
BWS
[3:0]
36
Control
Logic
36
Reg.
Reg.
Reg. 36
36
36
CQ
Q
[35:0]
Document Number: 001-57825 Rev. *N
Page 3 of 33
CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 8
Read Operations ......................................................... 8
Write Operations ......................................................... 9
Byte Write Operations ................................................. 9
Concurrent Transactions ............................................. 9
Depth Expansion ......................................................... 9
Programmable Impedance .......................................... 9
Echo Clocks ................................................................ 9
PLL .............................................................................. 9
Application Example ...................................................... 10
Truth Table ...................................................................... 11
Write Cycle Descriptions ............................................... 11
Write Cycle Descriptions ............................................... 12
Write Cycle Descriptions ............................................... 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port ....................................................... 13
Performing a TAP Reset ........................................... 13
TAP Registers ........................................................... 13
TAP Instruction Set ................................................... 13
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 16
TAP Electrical Characteristics ...................................... 16
TAP AC Switching Characteristics ............................... 17
TAP Timing and Test Conditions .................................. 18
Identification Register Definitions ................................ 19
Scan Register Sizes ....................................................... 19
Instruction Codes ........................................................... 19
Boundary Scan Order .................................................... 20
Power Up Sequence in QDR II SRAM ........................... 21
Power Up Sequence ................................................. 21
PLL Constraints ......................................................... 21
Maximum Ratings ........................................................... 22
Operating Range ............................................................. 22
Neutron Soft Error Immunity ......................................... 22
Electrical Characteristics ............................................... 22
DC Electrical Characteristics ..................................... 22
AC Electrical Characteristics ..................................... 24
Capacitance .................................................................... 24
Thermal Resistance ........................................................ 24
AC Test Loads and Waveforms ..................................... 24
Switching Characteristics .............................................. 25
Switching Waveforms .................................................... 27
Ordering Information ...................................................... 28
Ordering Code Definitions ......................................... 28
Package Diagram ............................................................ 29
Acronyms ........................................................................ 30
Document Conventions ................................................. 30
Units of Measure ....................................................... 30
Document History Page ................................................. 31
Sales, Solutions, and Legal Information ...................... 33
Worldwide Sales and Design Support ....................... 33
Products .................................................................... 33
PSoC®Solutions ....................................................... 33
Cypress Developer Community ................................. 33
Technical Support ..................................................... 33
Document Number: 001-57825 Rev. *N
Page 4 of 33
CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
Pin Configurations
The pin configurations for CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 follow.
[1]
Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1425KV18 (4M × 9)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/72M
NC
NC
D5
NC
NC
D6
V
REF
NC
NC
Q7
NC
D8
NC
TCK
3
A
NC
NC
NC
Q5
NC
Q6
V
DDQ
NC
NC
D7
NC
NC
Q8
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
NC
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/144M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
D3
NC
NC
V
REF
Q2
NC
NC
NC
NC
D0
TMS
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
Note
1. NC/72M, NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-57825 Rev. *N
Page 5 of 33
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