STA2058
TESEO™
GPS platform high-sensitivity baseband
Data Brief
Features
■
■
Single chip baseband with embedded Flash
Complete embedded memory system:
– Flash 256 KB +16 Kbytes
– RAM 64 Kbytes
66 MHz ARM7TDMI 32 bit processor
High performance GPS engine (HPGPS)
SBAS (WAAS and EGNOS) supported
Sensitivity (-146 dBm acquisition, -159 dBm
tracking)
Time to first fix (1s reacquisition, 2.5 s hot start,
34 s warm start, 39 s cold start)
Accuracy (2 m autonomous)
External memory interface (EMI) supporting up
to 64 Mbite of external SRAM, Flash and ROM
Extensive GPS receiver interfaces:
48 GPIOs, 4 UARTs, 2 SPIs, 2 I2Cs,
2 CANs 2.0, 1 USB 1.1,1 HDLC and 4 channels
ADC
ST proprietary Flash embedded technology
LFBGA144 and LQFP64 lead-free package
-40 °C to 85 °C operating temperature range
LQFP64
■
■
■
■
Evaluation kits
■
■
■
STA2058 module reference design (25x25mm)
Evaluation board hosting STA2058 module
SDK board (for application SW development)
■
Description
STA2058 is the high-sensitivity baseband of
TESEO GPS platform which include the STA5620
RF Front-End.
The embedded Flash memory enables the
equipment manufacturer to load the entire GPS
software (including tracking, acquisition,
navigation and data output) after customizing its
interfaces to his needs. A standard GPS library is
available from ST.
TESEO is the ideal solution for consumer,
handheld, PND (portable navigation), in vehicle
navigation and telematics systems.
SBAS (WAAS and EGNOS) feature is also
supported.
■
■
■
■
■
■
bs
O
et
l
o
ro
P
e
uc
d
s)
t(
O
-
so
b
te
le
ro
P
uc
d
LFBGA144
s)
t(
Table 1.
Device summary
Package
LQFP64 (10x10x1.4mm)
LQFP64 (10x10x1.4mm)
LFBGA144 (10x10x1.7mm)
LFBGA144 (10x10x1.7mm)
LFBGA144 (10x10x1.7mm)
LFBGA144 (10x10x1.7mm)
EMI
(External Memory Interface)
No
No
Yes
Yes
Yes
Yes
Packing
Tray
Tape and reel
Tray
Tape and reel
Tray
Tape and reel
Automotive
grade
No
No
No
No
Yes
Yes
Order code
STA2058
STA2058TR
STA2058EX
STA2058EXTR
STA2058EXA
STA2058EXATR
September 2013
Rev 4
1/20
www.st.com
20
For further information contact your local STMicroelectronics sales office.
Contents
STA2058
Contents
1
2
Features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
System block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1
3.2
3.3
Package LFBGA144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package LQFP64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Electrical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
DC electrical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
nRSTIN input filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Flash electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
LVD electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
bs
O
6
5
et
l
o
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ro
P
e
uc
d
s)
t(
O
-
so
b
te
le
ro
P
uc
d
s)
t(
GPS performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/20
STA2058
Features summary
1
Features summary
●
●
ARM7TDMI 16/32 bit RISC CPU based host microcontroller running at a frequency up
to 66 MHz.
Complete embedded memory system:
–
–
Flash 256 Kbytes + 16 Kbytes (100 KB erasing/programming cycles)
RAM 64 Kbytes.
●
●
●
●
●
●
●
External memory interface provides glueless support for up to four banks of external
SRAM, Flash, ROM.
High performance GPS engine (HPGPS).
ST Proprietary CMOS (0.18 µm) Flash embedded technology.
SBAS (WAAS and EGNOS) supported
-40 °C to 85 °C operating temperature range.
144-pin LFBGA package and 64-pin LQFP package
Power supply:
–
–
–
3.0 V to 3.6 V operating supply range for Input/Output periphery
3.0 V to 3.6 V operating supply range for A/D Converter reference
1.8 V operating supply range for core supply provided either by internal voltage
regulator (with external stabilization capacitor) or by external supply voltage.
●
Reset and clock control unit able to provide low power modes (WAIT, SLOW, STOP,
STANDBY) and to generate the internal clock from the external reference through
integrated PLL.
48 programmable general purpose I/O, each pin programmable independently as
digital input or digital output; 40 (30 in LQFP64) are multiplexed with peripheral
functions; 16 can generate an interrupt on input level/transition.
●
●
●
●
b
O
et
l
so
●
●
●
ro
P
e
Real time clock module with 32 kHz low power oscillator and separate power supply to
continue running during standby mode.
16-bit Watchdog timer with 8 bits prescaler for system reliability and integrity.
2 CAN modules compliant with the CAN specification V2.0 part B (active) and bit rate
can be programmed up to 1 MBaud. One additional CAN at 1 Mbps (for STA2058 EM
SIP version)
Four 16-bit programmable timers with 7 bit prescaler, up to two input capture/output
compare, one pulse counter function, one PWM channel with selectable frequency
each.
4 channels 12-bit sigma-delta analog to digital converter, single channel or multi
channel conversion modes, single-shot or continuous conversion modes, sample rate
1 kHz, conversion range 0-2.5 V .
Three serial communication interfaces (UART) allow full duplex, asynchronous,
communications with external devices, independently programmable TX and RX baud
rates up to 625 Kbaud.
One UART adapted to suit smart card interface needs, for asynchronous SC as defined
by ISO 7816-3. It includes SC clock generation.
Two serial peripheral interfaces (SPI) allow full duplex, synchronous communications
with external devices, master or slave operation, max baud rate of 5.5 Mb/s. One SPI
may be used as multimedia card interface.
uc
d
s)
t(
O
-
so
b
te
le
ro
P
uc
d
s)
t(
●
●
3/20
Features summary
●
STA2058
Two I
2
C Interfaces provide multi-master and slave functions, support normal and fast
I
2
C mode (400 KHz), 7/10 bit addressing modes. One I
2
C Interface is multiplexed with
one SPI, so either 2 x SPI + 1 x I
2
C or 1 x SPI + 2 x I
2
C may be used at a time.
Enhanced interrupt controller supports 32 interrupt vectors, independently maskable,
with interrupt vector table for faster response and 16 priority levels, software
programmable for each source. Up to 2 maskable interrupts may be mapped on FIQ.
Wakeup unit allows exiting from power down modes by detection of an event on two
external pins (one is active high and other is active low) or on internal real time clock
alarm.
USB unit V1.1 compliant, software configurable endpoint setting, USB suspend/resume
support
High level data link controller (HDLC) unit supports full duplex operating mode, NRZ,
NRZI, FM0 and MANCHESTER modes, and internal 8-bit baud rate generator.
●
●
●
●
bs
O
et
l
o
ro
P
e
uc
d
s)
t(
O
-
so
b
te
le
ro
P
uc
d
s)
t(
4/20
STA2058
Pin description
2
2.1
Pin description
Logic symbol
Figure 1.
STA2058 TESEO symbol
V18 (2)
V33 (7)
Power
Pads
VSS (10)
AVSS
AVDD
V18BKP
GPSCLK
Clock
& Reset
CK
CKOUT
RSTINn
A[23:0]
D[15:0]
WEn.[1:0]
CSn.[3:0]
RDn
P0.[15:0]
EMI
Interface
LFBGA144
ONLY
STA2058
TESEO
P1.[15:0]
JTAG
Port
JTDI
JTCK
JTMS
JTRSTn
JTDO
Debug
DBGRQS
BOOTEN
bs
O
et
l
o
ro
P
e
uc
d
s)
t(
O
-
so
b
te
le
P2.[15:0]
(LFBGA144 Only)
nSTDBY_I
nSTDBY_O
RTCXTO
RTCXTI
WAKEUP
nWAKEUP
ro
P
uc
d
GeneraI
Purpose I/O
s)
t(
RTC
& WKUP
Pads
USBDN
USBDP
USB Pads
GPSDAT[1] LFBGA144 Only
GPSDAT[0]
5/20
京公网安备 11010802033920号
EEWORLD
