IXDI509 / IXDN509
9 Ampere Low-Side Ultrafast MOSFET Drivers
Features
• Built using the advantages and compatibility
of CMOS and IXYS HDMOS
TM
processes
• Latch-Up protected up to 9 Amps
• High 9A peak output current
• Wide operating range: 4.5V to 30V
•
-55°C
to +125°C extended operating
temperature
• High capacitive load drive
capability: 1800pF in <15ns
• Matched rise and fall times
• Low propagation delay time
• Low output impedance
• Low supply current
General Description
The IXDI509 and IXDN509 are high speed high current gate
drivers specifically designed to drive the largest IXYS
MOSFETs & IGBTs to their minimum switching time and
maximum practical frequency limits. The IXDI509 and
IXDN509 can source and sink 9 Amps of peak current while
producing voltage rise and fall times of less than 30ns. The
inputs of the drivers are compatible with TTL or CMOS and
are virtually immune to latch up over the entire operating
range. Patented* design innovations eliminate cross
conduction and current "shoot-through". Improved speed
and drive capabilities are further enhanced by matched rise
and fall times.
The IXDI509 is configured as a Inverting Gate Driver, and the
IXDN509 is configured as a Non-Inverting Gate Driver.
The IXDI509 and IXDN509 are each available in the 8-Pin P-
DIP (PI) package, the 8-Pin SOIC (SIA) package, and the
6-Lead DFN (D1) package, (which occupies less than 65%
of the board area of the 8-Pin SOIC).
Applications
•
•
•
•
•
•
•
•
•
•
Driving MOSFETs and IGBTs
Motor controls
Line drivers
Pulse generators
Local power ON/OFF switch
Switch Mode Power Supplies (SMPS)
DC to DC converters
Pulse transformer driver
Class D switching amplifiers
Power charge pumps
*United States Patent 6,917,227
Ordering Information
Part Number
IXDI509PI
IXDI509SIA
IXDI509SIAT/R
IXDI509D1
IXDI509D1T/R
IXDN509PI
IXDN509SIA
IXDN509SIAT/R
IXDN509D1
IXDN509D1T/R
Description
9A Low Side Gate Driver I.C.
9A Low Side Gate Driver I.C.
9A Low Side Gate Driver I.C.
9A Low Side Gate Driver I.C.
9A Low Side Gate Driver I.C.
9A Low Side Gate Driver I.C.
9A Low Side Gate Driver I.C.
9A Low Side Gate Driver I.C.
9A Low Side Gate Driver I.C.
9A Low Side Gate Driver I.C.
Package
Type
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
6-Lead DFN
6-Lead DFN
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
6-Lead DFN
6-Lead DFN
Packing Style
Tube
Tube
13” Tape and Reel
2” x 2” Waffle Pack
13” Tape and Reel
Tube
Tube
13” Tape and Reel
2” x 2” Waffle Pack
13” Tape and Reel
Pack
Qty
50
94
2500
56
2500
50
94
2500
56
2500
Configuration
Inverting
Non-Inverting
NOTE:
All parts are lead-free and RoHS Compliant
Copyright © 2007 IXYS CORPORATION All rights reserved
DS99670A(10/07)
First Release
IXDI509 / IXDN509
Figure 1 - IXDI509 Inverting 9A Gate Driver Functional Block Diagram
Vcc
Vcc
P
IN
ANTI-CROSS
CONDUCTION
CIRCUIT *
N
OUT
GND
GND
Figure 2 - IXDN509 Non-Inverting 9A Gate Driver Functional Block Diagram
Vcc
Vcc
P
IN
ANTI-CROSS
CONDUCTION
CIRCUIT *
N
OUT
GND
GND
* United States Patent 6,917,227
Copyright © 2007 IXYS CORPORATION All rights reserved
2
IXDI509 / IXDN509
Absolute Maximum Ratings
(1)
Parameter
Supply Voltage
All Other Pins
Junction Temperature
Storage Temperature
Lead Temperature (10 Sec)
Value
35 V
-0.3 V to V
CC
+ 0.3V
150
°
C
-65
°
C to 150
°
C
300
°
C
Operating Ratings
(2)
Parameter
Value
Operating Supply Voltage
4.5V to 30V
Operating Temperature Range
-55
°
C to 125
°
C
Package Thermal Resistance
*
θ
J-A
(typ) 125
°
C/W
8-PinPDIP
(PI)
8-Pin SOIC
(SIA)
θ
J-A
(typ) 200
°
C/W
6-Lead DFN
(D1)
θ
J-A
(typ) 125-200
°
C/W
θ
J-C
(max) 2.0
°
C/W
6-Lead DFN
(D1)
6-Lead DFN
(D1)
θ
J-S
(typ)
6.3 °
C/W
Electrical Characteristics @ T
A
= 25
o
C
(3)
Unless otherwise noted, 4.5V
≤
V
CC
≤
30V .
All voltage measurements with respect to GND. IXD_509 configured as described in
Test Conditions.
(4)
Symbol
V
IH
V
IL
V
IN
I
IN
V
OH
V
OL
R
OH
R
OL
I
PEAK
I
DC
t
R
t
F
t
ONDLY
t
OFFDLY
V
CC
I
CC
Parameter
High input voltage
Low input voltage
Input voltage range
Input current
High output voltage
Low output voltage
High state output resistance
Low state output resistance
Peak output current
Continuous output current
Rise time
Fall time
On-time propagation delay
Off-time propagation delay
Power supply voltage
Power supply current
Test Conditions
4.5V
≤
V
CC
≤
18V
4.5V
≤
V
CC
≤
18V
Min
2.4
Typ
Max
0.8
Units
V
V
V
µA
V
V
Ω
Ω
A
-5
0V
≤
V
IN
≤
V
CC
-10
V
CC
- 0.025
V
CC
+ 0.3
10
0.025
V
CC
= 18V
V
CC
= 18V
V
CC
= 15V
Limited by package power
dissipation
C
LOAD
=10,000pF V
CC
=18V
C
LOAD
=10,000pF V
CC
=18V
C
LOAD
=10,000pF V
CC
=18V
C
LOAD
=10,000pF V
CC
=18V
4.5
V
CC
= 18V, V
IN
=0V
V
IN
= 3.5V
V
IN
= V
CC
0.6
0.4
9
1
0.8
2
25
23
18
19
18
1
45
40
35
30
30
75
3
75
A
ns
ns
ns
ns
V
µA
mA
mA
IXYS reserves the right to change limits, test conditions, and dimensions.
3
IXDI509 / IXDN509
Electrical Characteristics @ temperatures over -55
o
C to 125
o
C
(3)
Unless otherwise noted, 4.5V
≤
V
CC
≤
30V , Tj < 150
o
C
All voltage measurements with respect to GND. IXD_502 configured as described in
Test Conditions.
All specifications are for one channel.
(4)
Symbol
V
IH
V
IL
V
IN
I
IN
V
OH
V
OL
R
OH
R
OL
I
DC
t
R
t
F
t
ONDLY
t
OFFDLY
V
CC
I
CC
Parameter
High input voltage
Low input voltage
Input voltage range
Input current
High output voltage
Low output voltage
High state output resistance
Low state output resistance
Continuous output current
Rise time
Fall time
On-time propagation delay
Off-time propagation delay
Power supply voltage
Power supply current
Test Conditions
4.5V
≤
V
CC
≤
18V
4.5V
≤
V
CC
≤
18V
Min
2.4
Typ
Max
0.8
Units
V
V
V
µA
V
V
Ω
Ω
A
ns
ns
ns
ns
V
µA
mA
mA
-5
0V
≤
V
IN
≤
V
CC
-10
V
CC
– 0.025
V
CC
+ 0.3
10
0.025
V
CC
= 18V
V
CC
= 18V
C
LOAD
=10,000pF V
CC
=18V
C
LOAD
=10,000pF V
CC
=18V
C
LOAD
=10,000pF V
CC
=18V
C
LOAD
=10,000pF V
CC
=18V
4.5
V
CC
=18V, V
IN
= 0V
V
IN
= 3.5V
V
IN
= V
CC
18
2
1.5
1
60
60
55
40
30
0.13
3
0.13
Notes:
1. Operating the device beyond the parameters listed as “Absolute Maximum Ratings” may cause permanent damage
to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
2. The device is not intended to be operated outside of the Operating Ratings.
3. Electrical Characteristics provided are associated with the stated Test Conditions.
4. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily to
highlight any specific performance limits within which the device is guaranteed to function.
The following notes are meant to define the conditions for the
θ
J-A
,
θ
J-C
and
θ
J-S
values:
1) The
θ
J-A
(typ) is defined as junction to ambient. The
θ
J-A
of the standard single die 8-Lead PDIP and 8-Lead SOIC are dominated by the
resistance of the package, and the IXD_5XX are typical. The values for these packages are natural convection values with vertical boards
and the values would be lower with forced convection. For the 6-Lead DFN package, the
θ
J-A
value supposes the DFN package is
soldered on a PCB. The
θ
J-A
(typ) is 200
°
C/W with no special provisions on the PCB, but because the center pad provides a low
thermal resistance to the die, it is easy to reduce the
θ
J-A
by adding connected copper pads or traces on the PCB. These can reduce
the
θ
J-A
(typ) to 125
°
C/W easily, and potentially even lower. The
θ
J-A
for DFN on PCB without heatsink or thermal management will
vary significantly with size, construction, layout, materials, etc. This typical range tells the user what he is likely to get if he does no
thermal management.
2)
θ
J-C
(max) is defined as juction to case, where case is the large pad on the back of the DFN package. The
θ
J-C
values are generally not
published for the PDIP and SOIC packages. The
θ
J-C
for the DFN packages are important to show the low thermal resistance from junction to
the die attach pad on the back of the DFN, -- and a guardband has been added to be safe.
3) The
θ
J-S
(typ) is defined as junction to heatsink, where the DFN package is soldered to a thermal substrate that is mounted on a heatsink.
The value must be typical because there are a variety of thermal substrates. This value was calculated based on easily available IMS in the
U.S. or Europe, and not a premium Japanese IMS. A 4 mil dialectric with a thermal conductivity of 2.2W/mC was assumed. The result was
given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential low thermal resistance for the
DFN package.
*
Copyright © 2007 IXYS CORPORATION All rights reserved
4
IXDI509 / IXDN509
Pin Description
PIN
1, 8
2
6, 7
SYMBOL
V
CC
IN
OUT
FUNCTION
Supply Voltage
Input
Output
DESCRIPTION
Power supply input voltage. These pins provide power to the
entire device. The range for this voltage is 4.5V to 30V.
Input drive signal, TTL or CMOS compatible.
Driver output. For application purposes, these pins are
connected, through a resistor, to the gate of a MOSFET/IGBT.
The device ground pins. Internally connected to all circuitry,
these pins provide ground reference for the entire chip and
should be connected to a low noise analog ground plane for
optimum performance.
4, 6
GND
Ground
CAUTION: Follow proper ESD procedures when handling and assembling this component.
Pin Configurations
8 PIN DIP (PI)
8 PIN SOIC (SIA)
V
CC
IN
N/C
GND
1
2
3
4
I
X
D
I
5
0
9
8
7
6
5
V
CC
OUT
OUT
GND
V
CC
IN
N/C
GND
1
2
3
4
8 PIN DIP (PI)
8 PIN SOIC (SIA)
I
X
D
N
5
0
9
8
7
6
5
V
CC
OUT
OUT
GND
6 LEAD DFN (D1)
(Bottom View)
I
X
D
I
5
0
9
6 LEAD DFN (D1)
(Bottom View)
I
X
D
N
5
0
9
V
CC
OUT
GND
6
5
4
1
IN
2
N/C
3
GND
V
CC
OUT
GND
6
5
4
1
IN
2
N/C
3
GND
NOTE:
Solder tabs on bottom of DFN packages are grounded
Figure 3 - Characteristics Test Diagram
5.0V
0V
10uF
25V
Vcc
0V
IXDI414
IXDI509
Vcc
0V
IXDN414
IXDN509
2500 pf
C
LOAD
15nF
IXD_509
Agilent 1147A
Current Probe
5
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