Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
OM5232
DESCRIPTION
The OM5232 Single-Chip 8-Bit Microcontroller is manufactured in an
advanced CMOS process and is a derivative of the 80C51
microcontroller family. The OM5232 has the same instruction set as
the 80C51.
See also:
– OM5202 — ROMless version
– OM5234 — 16K bytes mask programmable ROM
– OM5238 — 32K bytes mask programmable ROM
This device provides architectural enhancements that make it
applicable in a variety of applications for general control systems.
The OM5232 contains a non-volatile 8k
×
8 read-only program
memory, a volatile 256
×
8 read/write data memory, four 8-bit I/O
ports, two 16-bit timer/event counters (identical to the timers of the
80C51), a multi-source, two-priority-level, nested interrupt structure,
UART and on-chip oscillator and timing circuits. For systems that
require extra capability, the OM5232 can be expanded using
standard TTL compatible memories and logic.
The device also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic plus bit-handling
capabilities. The instruction set consists of over 100 instructions: 49
one-byte, 45 two-byte and 17 three-byte. With a 16MHz crystal, 58%
of the instructions are executed in 0.75µs and 40% in 1.5µs. Multiply
and divide instructions require 3µs.
PIN CONFIGURATIONS
P1.0 1
P1.1 2
P1.2 3
P1.3 4
P1.4 5
P1.5 6
P1.6 7
P1.7 8
RST 9
RxD/P3.0 10
TxD/P3.1 11
INT0/P3.2 12
INT1/P3.3 13
T0/P3.4 14
T1/P3.5 15
WR/P3.6 16
RD/P3.7 17
XTAL2 18
XTAL1 19
V
SS
20
DIP
40 V
DD
39 P0.0/AD0
38 P0.1/AD1
37 P0.2/AD2
36 P0.3/AD3
35 P0.4/AD4
34 P0.5/AD5
33 P0.6/AD6
32 P0.7/AD7
31 EA
30 ALE
29 PSEN
28 P2.7/A15
27 P2.6/A14
26 P2.5/A13
25 P2.4/A12
24 P2.3/A11
23 P2.2/A10
22 P2.1/A9
21 P2.0/A8
FEATURES
•
80C51 central processing unit
•
8k
×
8 ROM, expandable externally to 64k bytes
•
256
×
8 RAM, expandable externally to 64k bytes
•
Two standard 16-bit timer/counters
•
Four 8-bit I/O ports
•
Two open drain I/O’s (P1.6, P1.7)
•
Full-duplex UART facilities
•
Power control modes
–
Idle mode
–
Power-down mode
44
34
1
33
QFP
(SOT307–2)
11
23
•
ROM code protection
•
Extended frequency range: 1.2 to 16 MHz
•
Operating ambient temperature range: 0 to
PART NUMBER SELECTION
PHILIPS PART
ORDER NUMBER
PART MARKING
OM5232/FBP/xxx
1)
1)
12
22
+70°C
SEE PAGE 2 FOR QFP PIN FUNCTIONS.
PACKAGE NUMBER
SOT129
TEMPERATURE RANGE
°
C,
PACKAGE
0 to +70, Plastic Dual In–line Package, 40 leads
0 to +70, Plastic Quad Flat Pack, 44 leads
FREQUENCY
MHz
1.2 to 16
1.2 to 16
OM5232/FBB/xxx
SOT307–2
NOTE:
1. xxx denotes the ROM code number.
EQUIVALENT TYPES
Details are as specified by the data sheet for the equivalent type:
OM5202 = P80C652 without I
2
C function.
OM5232 = P83C652 without I
2
C function.
OM5234 = P83C654 without I
2
C function.
OM5238 = P83C528 without I
2
C function.
December 1994
1
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
OM5232
QFP PIN FUNCTIONS
44
34
LOGIC SYMBOL
V
DD
V
SS
ADDRESS AND
DATA BUS
ADDRESS BUS
RST
1
33
QFP
(SOT307–2)
11
23
ALTERNATE
FUNCTIONS
XTAL1
XTAL2
EA
PSEN
ALE
12
22
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Function
P1.5
P1.6
P1.7
RST
P3.0/RxD
V
SS4
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Function
V
SS1
NC
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE
V
SS2
EA/V
PP
P0.7/AD7
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
V
DD
V
SS3
P1.0
P1.1
P1.2
P1.3
P1.4
RxD
TxD
INT0
INT1
T0
T1
WR
RD
PORT 3
NOTE:
1. Due to EMC improvements, all V
SS
pins (6, 16, 28, 39) must be
connected to V
SS
.
BLOCK DIAGRAM
FREQUENCY
REFERENCE
XTAL2
XTAL1
COUNTERS
T0
T1
OSCILLATOR
AND
TIMING
PROGRAM
MEMORY
(8K x 8 ROM)
DATA
MEMORY
(256 x 8 RAM)
TWO 16-BIT
TIMER/EVENT
COUNTERS
CPU
INTERNAL
INTERRUPTS
64K BYTE BUS
EXPANSION
CONTRTOL
PROGRAMMABLE I/O
PROG SERIAL PORT
FULL DUPLEX UART
SYNCHRONOUS SHIFT
INT0
INT1
CONTROL
PARALLEL PORTS,
ADDRESS/DATA BUS
AND I/O PINS
SERIAL IN
SERIAL OUT
EXTERNAL
INTERRUPTS
SHARED WITH
PORT 3
December 1994
2
PORT 2
PORT 1
PORT 0
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
OM5232
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC
V
SS
V
DD
P0.0–0.7
DIP
20
40
39–32
QFP
6, 16,
28, 39
38
37–30
TYPE
I
I
I/O
NAME AND FUNCTION
Ground:
0V reference. With the QFP package all V
SS
pins (V
SS1
to V
SS4
) must be connected.
Power Supply:
This is the power supply voltage for normal, idle, and power-down operation.
Port 0:
Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them
float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address
and data bus during accesses to external program and data memory. In this application, it uses
strong internal pull-ups when emitting 1s.
Port 1:
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7 which
are open drain. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current
because of the internal pull-ups. (See DC Electrical Characteristics: I
IL
). Alternate functions
include:
open drain output
open drain output
Port 2:
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port
2 pins that are externally being pulled low will source current because of the internal pull-ups.
(See DC Electrical Characteristics: I
IL
). Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to external data memory that use 16-bit
addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s.
During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the
contents of the P2 special function register.
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port
3 pins that are externally being pulled low will source current because of the pull-ups. (See DC
Electrical Characteristics: I
IL
). Port 3 also serves the special features of the 80C51 family, as
listed below:
RxD (P3.0):
Serial input port
TxD (P3.1):
Serial output port
INT0 (P3.2):
External interrupt
INT1 (P3.3):
External interrupt
T0 (P3.4):
Timer 0 external input
T1 (P3.5):
Timer 1 external input
WR (P3.6):
External data memory write strobe
RD (P3.7):
External data memory read strobe
Reset:
A high on this pin for two machine cycles while the oscillator is running, resets the device.
An internal diffused resistor to V
SS
permits a power-on reset using only an external capacitor to
V
DD
.
Address Latch Enable:
Output pulse for latching the low byte of the address during an access
to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator
frequency. Note that one ALE pulse is skipped during each access to external data memory.
Program Store Enable:
Read strobe to external program memory via Port 0 and Port 2. It is
activated twice each machine cycle during fetches from the external program memory. When
executing out of external program memory two activations of PSEN are skipped during each
access to external data memory. PSEN is not activated (remains HIGH) during no fetches from
external program memory. PSEN can sink/source 8 LSTTL inputs and can drive CMOS inputs
without external pull–ups.
External Access:
If during a RESET, EA is held at TTL, level HIGH, the CPU executes out of the
internal program memory ROM provided the Program Counter is less than 16384. If during a
RESET, EA is held a TTL LOW level, the CPU executes out of external program memory. EA is
not allowed to float.
Crystal 1:
Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
Crystal 2:
Output from the inverting oscillator amplifier.
P1.0–P1.5
1–6
40–44,
1
I/O
P1.6
P1.7
P2.0–P2.7
7
8
21–28
2
3
18–25
I/O
I/O
I/O
P3.0–P3.7
10–17
5,
7–13
I/O
10
11
12
13
14
15
16
17
RST
9
5
7
8
9
10
11
12
13
4
I
O
I
I
I
I
O
O
I
ALE
30
27
I/O
PSEN
29
26
O
EA
31
29
I
XTAL1
XTAL2
19
18
15
14
I
O
NOTE:
To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than V
DD
+ 0.5V or V
SS
– 0.5V, respectively.
December 1994
3
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
OM5232
Table 1.
SYMBOL
ACC*
B*
DPTR:
DPH
DPL
OM5232 Special Function Registers
DESCRIPTION
Accumulator
B Register
Data Pointer
(2 bytes)
Data Pointer High
Data Pointer Low
DIRECT
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
ADDRESS MSB
LSB
E0H
F0H
E7
F7
E6
F6
E5
F5
E4
F4
E3
F3
E2
F2
E1
F1
E0
F0
RESET
VALUE
00H
00H
83H
82H
AF
AE
AD
ES1
BE
BD
PS1
86
AD6
96
SCL
A6
A14
B6
WR
–
9E
SM1
A5
A13
B5
T1
–
9D
SM2
A4
A12
B4
T0
–
9C
REN
A3
A11
B3
INT1
GF1
9B
TB8
A2
A10
B2
INT0
GF0
9A
RB8
A1
A9
B1
TXD
PD
99
TI
A0
A8
B0
RXD
IDL
98
RI
85
AD5
95
AC
ES0
BC
PS0
84
AD4
94
AB
ET1
BB
PT1
83
AD3
93
AA
EX1
BA
PX1
82
AD2
92
A9
ET0
B9
PT0
81
AD1
91
A8
EX0
B8
PX0
80
AD0
90
00H
00H
IE*#
Interrupt Enable
A8H
EA
BF
0x000000B
IP*#
Interrupt Priority
B8H
–
87
xx000000B
P0*
Port 0
80H
AD7
97
FFH
P1*#
Port 1
90H
SDA
A7
FFH
P2*
Port 2
A0H
A15
B7
FFH
P3*
PCON
Port 3
Power Control
B0H
87H
RD
SMOD
9F
FFH
0xxx0000B
S0CON*#
S0BUF#
Serial 0 Port Control
Serial 0 Data Buffer
98H
99H
SM0
00H
xxxxxxxxB
D7
PSW*
Program Status Word
reserved (Note 1)
SP
Stack Pointer
reserved (Note 1)
D0H
DAH
81H
DBH
CY
D6
AC
D5
F0
D4
RS1
D3
RS0
D2
OV
D1
F1
D0
P
00H
00H
07H
00H
reserved (Note 1)
D9H
F8H
reserved (Note 1)
D8H
8F
8E
TR1
8D
TF0
8C
TR0
8B
IE1
8A
IT1
89
IE0
88
IT0
00000000B
TCON*
TH1
TH0
TL1
TL0
TMOD
*
Timer Control
Timer High 1
Timer High 0
Timer Low 1
Timer Low 0
Timer Mode
88H
8DH
8CH
8BH
8AH
89H
TF1
00H
00H
00H
00H
00H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
NOTE
1. Reserved for I
2
C; not supported in OM5232
December 1994
4
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
OM5232
ROM CODE PROTECTION
The OM5232 has an additional security feature. ROM code
protection may be selected by setting a mask–programmable
security bit (i.e., user dependent). This feature may be requested
during ROM code submission. When selected, the ROM code is
protected and cannot be read out at any time by any test mode or by
any instruction in the external program memory space.
The MOVC instructions are the only instructions that have access to
program code in the internal or external program memory. The EA
input is latched during RESET and is “don’t care” after RESET
(also if the security bit is not set). This implementation prevents
reading internal program code by switching from external program
memory to internal program memory during a MOVC instruction or
any other instruction that uses immediate data.
Reset
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
V
DD
and RST must come up at the same time for a proper start-up.
Idle Mode
In the idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
idle mode is activated. The CPU contents, the on-chip RAM, and all
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol, page 2.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
Power-Down Mode
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
reset is the only way to terminate the power-down mode. The control
bits for the reduced power modes are in the special function register
PCON. Table 2 shows the state of the I/O ports during low current
operating modes.
Table 2.
MODE
Idle
Idle
External Pin Status During Idle and Power-Down Mode
PROGRAM
MEMORY
Internal
External
Internal
External
ALE
1
1
0
0
PSEN
1
1
0
0
PORT 0
Data
Float
Data
Float
PORT 1
Data
Data
Data
Data
PORT 2
Data
Address
Data
Data
PORT 3
Data
Data
Data
Data
Power-down
Power-down
Serial Control Register (S1CON) – See Table 3
S1CON (D8H)
CR2
ENS1
STA
STO
SI
AA
CR1
CR0
Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.
Table 3.
CR2
0
0
0
0
1
1
1
1
Serial Clock Rates
BIT FREQUENCY (kHz) AT f
OSC
CR1
0
0
1
1
0
0
1
1
CR0
0
1
0
1
0
1
0
1
6MHz
23
27
31.25
37
6.25
50
100
0.24 < 62.5
0 to 255
12MHz
47
54
62.5
75
12.5
100
200
0.49 < 62.5
0 to 254
16MHz
62.5
71
83.3
100
17
133
267
0.65 < 55.6
0 to 253
f
OSC
DIVIDED BY
256
224
192
160
960
120
60
96
×
(256 – (reload value Timer 1))
reload value range Timer 1 (in mode 2)
December 1994
5
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