Chip Schottky Barrier Diodes
FM120-LN THRU FM1100-LN
Silicon epitaxial planer type
Formosa MS
SMA-LN
0.205(5.2)
0.189(4.8)
0.012(0.3) Typ.
Features
Plastic package has Underwriters Laboratory
Flammability Classification 94V-O Utilizing Flame
Retardant Epoxy M
olding Compound.
For surface mounted applications.
Exceeds environmental standards of MIL-S-19500 /
228
Low leakage current.
0.040(1.0) Typ.
0.110(2.8)
0.094(2.4)
0.181(4.6)
0.165(4.2)
0.075(1.9)
0.067(1.7)
0.040 (1.0) Typ.
0.067(1.7)
0.053(1.3)
Mechanical data
Case : Molded plastic, JEDEC DO-214AC
Terminals : Solder plated, solderable per MIL-STD-750,
Method 2026
Polarity : Indicated by c athode band
Mounting P
osition : Any
Weight : 0.0015 ounce, 0.05 gram
Dimensions in inches and (millimeters)
MAXIMUM RATINGS
(AT T
A
=25
o
C unless otherwise noted)
PARAMETER
Forward rectified current
Forward surge current
See Fig.1
8.3ms single half sine-wave superimposed on
rate load (JEDEC methode)
V
R
= V
RRM
T
A
=
25
o
C
o
CONDITIONS
Symbol
I
O
I
FSM
MIN.
TYP.
MAX.
1.0
30
0.5
10
UNIT
A
A
mA
mA
o
Reverse current
Thermal resistance
Diode junction capacitance
Storage temperature
I
R
Rq
JA
C
J
T
STG
-55
88
120
V
R
= V
RRM
T
A
= 125 C
Junction to ambient
f=1MHz and applied 4vDC reverse voltage
C / w
pF
+150
o
C
SYMBOLS
MARKING
CODE
SS12
SS13
SS14
SS15
SS16
SS18
S110
V
RRM
*1
V
RMS
*2
V
R
*3
V
F
*4
Operating
temperature
(
o
C)
(V)
FM120-LN
FM130-LN
FM140-LN
FM150-LN
FM160-LN
FM180-LN
FM1100-LN
20
30
40
50
60
80
100
(V)
14
21
28
35
42
56
70
(V)
20
30
40
50
60
80
100
(V)
0.50
-55 to +125
*1 Repetitive peak reverse voltage
0.70
-55 to +150
0.85
*2 RMS voltage
*3 Continuous reverse voltage
*4 Maximum forward voltage
RATING AND CHARACTERISTIC CURVES (FM120-LN THRU FM1100-LN)
FIG.1-TYPICAL FORWARD CURRENT DERATING CURVE
AVERAGE FORWARD CURRENT,(A)
FIG.2-TYPICAL FORWARD
CHARACTERISTICS
1.2
1.0
50
INSTANTANEOUS FORWARD CURRENT,(A)
FM
12
0-
LN
~F
FM
M
15
14
0-
0-
LN
LN
~F
M
16
0-
LN
0.8
15
FM
0.6
0.4
0.2
0
0
20
40
60
80
10
3.0
1.0
AMBIENT TEMPERATURE,( C)
FIG.3-MAXIMUM NON-REPETITIVE FORWARD
SURGE CURRENT
30
12
FM
LN
0-
10
M1
~F
0-
-L
N
LN
100
M1
~F
LN
0-
40
120
140
160
180
200
18
FM
L
0-
N
00
11
M
~F
-L
N
Tj=25 C
Pulse Width 300us
1% Duty Cycle
0.1
PEAK FORWARD SURGE CURRENT,(A)
24
.01
.1
.3
.5
.7
.9
1.1
1.3
1.5
18
Tj=25 C
8.3ms Single Half
Sine Wave
JEDEC method
FORWARD VOLT
AGE,(V)
12
6
FIG.5 - TYPICAL REVERSE
0
1
5
10
50
100
CHARACTERISTICS
100
NUMBER OF CYCLES AT 60Hz
FIG.4-TYPICAL JUNCTION CAPACITANCE
350
300
250
200
150
100
50
0
JUNCTION CAPACITANCE,(pF)
REVERSE LEAKAGE CURRENT, (mA)
10
1.0
Tj=75 C
.1
Tj=25 C
.01
.05
.1
.5
1
5
10
50
100
.01
0
20
40
60
80
100 120 140
REVERSE VOLTAGE,(V)
PERCENT OF RATED PEAK REVERSE VOLTAGE,(%)
FPGA/CPLD
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