oH
V SC
AV ER OM
AI SIO PL
LA N IA
BL S NT
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TISP4072F3LM THRU TISP4082F3LM,
TISP4125F3LM THRU TISP4180F3LM,
TISP4240F3LM THRU TISP4380F3LM
BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS
*R
TISP4xxxF3LM Overvoltage Protector Series
Ion-Implanted Breakdown Region
Precise and Stable Voltage
Low Voltage Overshoot under Surge
LM Package (Top View)
Device
‘4072
‘4082
‘4125
‘4150
‘4180
‘4240
‘4260
‘4290
‘4320
‘4380
V
DRM
V
58
66
100
120
145
180
200
220
240
270
V
(BO)
V
72
82
125
150
180
240
260
290
320
380
T(A)
NC
R(B)
1
2
3
MD4XAT
NC - No internal connection on pin 2
LMF Package (LM Package with Formed Leads) (Top View)
T(A)
NC
R(B)
1
2
3
MD4XAKB
Rated for International Surge Wave Shapes
NC - No internal connection on pin 2
Waveshape
10/160
µs
0.5/700
µs
10/700
µs
10/560
µs
10/1000
µs
Standard
FCC Part 68
I3124
ITU-T K.20/21
FCC Part 68
REA PE-60
I
TSP
A
60
38
50
45
35
Device Symbol
T
.............................................. UL Recognized Component
R
SD4XAA
Terminals T and R correspond to the
alternative line designators of A and B
Description
These devices are designed to limit overvoltages on the telephone line. Overvoltages are normally caused by a.c. power system or lightning
flash disturbances which are induced or conducted on to the telephone line. A single device provides 2-point protection and is typically used
for the protection of 2-wire telecommunication equipment (e.g. between the Ring to Tip wires for telephones and modems). Combinations of
devices can be used for multi-point protection (e.g. 3-point protection between Ring, Tip and Ground).
The protector consists of a symmetrical voltage-triggered bidirectional thyristor. Overvoltages are initially clipped by breakdown clamping until
the voltage rises to the breakover level, which causes the device to crowbar into a low-voltage on state. This low-voltage on state causes the
current resulting from the overvoltage to be safely diverted through the device. The high crowbar holding current prevents d.c. latchup as the
diverted current subsides.
How To Order
For Standard
Termination Finish
Order As
TISP4xxxF3LM
TISP4xxxF3LMR
For Lead Free
Termination Finish
Order As
TISP4xxxF3LM-S
TISP4xxxF3LMR-S
TISP4xxxF3LMFRS
Device
TISP4xxxF3LM
Package
Straight Lead DO-92 (LM)
Carrier
Bulk Pack
Tape and Reeled
Formed Lead DO-92 (LMF) Tape and Reeled TISP4xxxF3LMFR
Insert xxx value corresponding to protection voltages of 072, 082, 125 etc.
*RoHS Directive 2002/95/EC Jan 27 2003 including Annex
NOVEMBER 1997 - REVISED FEBRUARY 2005
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
TISP4xxxF3LM Overvoltage Protector Series
Description (continued)
This TISP4xxxF3LM range consists of ten voltage variants to meet various maximum system voltage levels (58 V to 270 V). They are guaran-
teed to voltage limit and withstand the listed international lightning surges in both polarities. These protection devices are supplied in a DO-92
(LM) cylindrical plastic package. The TISP4xxxF3LM is a straight lead DO-92 supplied in bulk pack and on tape and reeled. The
TISP4xxxF3LMF is a formed lead DO-92 supplied only on tape and reeled.
Absolute Maximum Ratings, TA = 25
°C
(Unless Otherwise Noted)
Rating
‘4072
‘4082
‘4125
‘4150
‘4180
‘4240
‘4260
‘4290
‘4320
‘4380
Symbol
Value
±
58
±
66
±
100
±
120
±
145
±
180
±
200
±
220
±
240
±
270
175
120
60
50
38
38
50
45
35
80
70
4
250
-40 to +150
-55 to +150
Unit
Repetitive peak off-state voltage (0
°C
< T
J
< 70
°C)
V
DRM
V
Non-repetitive peak on-state pulse current (see Notes 1, 2 and 3)
2/10
µs
(FCC Part 68, 2/10
µs
voltage wave shape) excluding ‘4072 - ‘4082
8/20
µs
(ANSI C62.41, 1.2/50
µs
voltage wave shape) excluding ‘4072 - ‘4082
10/160
µs
(FCC Part 68, 10/160
µs
voltage wave shape)
5/200
µs
(VDE 0433, 2 kV, 10/700
µs
voltage wave shape)
0.2/310
µs
(I3124, 1.5 kV, 0.5/700
µs
voltage wave shape)
5/310
µs
(ITU-T K.20/21, 1.5 kV, 10/700
µs
voltage wave shape)
5/310
µs
(FTZ R12, 2 kV, 10/700
µs
voltage wave shape)
10/560
µs
(FCC Part 68, 10/560
µs
voltage wave shape)
10/1000
µs
(REA PE-60, 10/1000
µs
voltage wave shape)
2/10
µs
(FCC Part 68, 2/10
µs
voltage wave shape) ‘4072 - ‘4082 only
8/20
µs
(ANSI C62.41, 1.2/50
µs
voltage wave shape) ‘4072 - ‘4082 only
Non-repetitive peak on-state current (see Notes 2 and 3)
50/60 Hz, 1 s
Initial rate of rise of on-state current, Linear current ramp, Maximum ramp value < 38 A
Junction temperature
Storage temperature range
NOTES: 1. Initially the TISP must be in thermal equilibrium with 0
°C
< T
J
< 70
°C.
2. The surge may be repeated after the TISP returns to its initial conditions.
3. Above 70
°C,
derate linearly to zero at 150
°C
lead temperature.
I
TSP
A
I
TSM
di
T
/dt
T
J
T
stg
A
A/µs
°C
°C
NOVEMBER 1997 - REVISED FEBRUARY 2005
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
TISP4xxxF3LM Overvoltage Protector Series
Electrical Characteristics for R and T Terminals, TJ = 25
°C
(Unless Otherwise Noted)
Parameter
Repetitive peak off-
state current
Test Conditions
V
D
=
±V
DRM
, 0
°C
< T
J
< 70
°C
‘4072
‘4082
‘4125
‘4150
‘4180
‘4240
‘4260
‘4290
‘4320
‘4380
‘4072
‘4082
‘4125
‘4150
‘4180
‘4240
‘4260
‘4290
‘4320
‘4380
±0.15
±0.15
±5
±10
108
74
74
40
25
20
Min
Typ
Max
±10
±72
±82
±125
±150
±180
±240
±260
±290
±320
±380
±86
±96
±143
±168
±198
±267
±287
±317
±347
±407
±0.6
±3
Unit
µA
I
DRM
V
(BO)
Breakover voltage
dv/dt =
±250
V/ms, R
SOURCE
= 300
Ω
V
V
(BO)
Impulse breakover
voltage
dv/dt =
±1000
V/µs, R
SOURCE
= 50
Ω
di/dt < 20 A/µs
V
I
(BO)
V
T
I
H
dv/dt
I
D
Breakover current
On-state voltage
Holding current
Critical rate of rise of
off-state voltage
Off-state current
dv/dt =
±250
V/ms, R
SOURCE
= 300
Ω
I
T
=
±5
A, t
W
= 100
µs
I
T
=
±5
A, di/dt = - /+ 30 mA/ms
Linear voltage ramp, Maximum ramp value < 0.85V
DRM
V
D
=
±50
V
f = 100 kHz, V
d
= 1 V r.m.s., V
D
= 0,
A
V
A
kV/µs
µA
C
off
Off-state capacitance
f = 100 kHz, V
d
= 1 V r.m.s., V
D
= -50 V
‘4072 - ‘4082
‘4125 - ‘4180
‘4240 - ‘4380
‘4072 - ‘4082
‘4125 - ‘4180
‘4240 - ‘4380
63
43
44
25
15
11
pF
Thermal Characteristics
Parameter
R
Θ
JA
Junction to free air thermal resistance
Test Conditions
EIA/JESD51-3 PCB mounted in an EIA/
JESD51-2 enclosure
Min
Typ
Max
120
Unit
°C/W
NOVEMBER 1997 - REVISED FEBRUARY 2005
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
TISP4xxxF3LM Overvoltage Protector Series
Parameter Measurement Information
+i
I
TSP
Quadrant I
Switching
Characteristic
I
TSM
I
T
V
T
I
H
I
DRM
-v
V
DRM
I
DRM
I
H
V
D
I
D
I
D
V
D
V
DRM
+v
V
(BO)
I
(BO)
I
(BO)
V
(BO)
V
T
I
T
I
TSM
Quadrant III
Switching
Characteristic
I
TSP
-i
PMXXAAB
Figure 1. Voltage- Current Characteristic for R and T Terminals
All Measurements are Referenced to the T Terminal
NOVEMBER 1997 - REVISED FEBRUARY 2005
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
TISP4xxxF3LM Overvoltage Protector Series
Typical Characteristics
OFF-STATE CURRENT
vs
JUNCTION TEMPERATURE
VDRM DERATING FACTOR
vs
MINIMUM AMBIENT TEMPERATURE
100
TC4XAA
1.00
TC4XAB
10
I
D
- Off-State Current -
µA
0.99
Derating Factor
1
0.98
'4072
AND
'4082
'4125
THRU
'4180
V
D
= 50 V
V
D
= -50 V
0·1
0.97
0·01
0.96
'4240
THRU
'4380
-35
-30
-25
-20
-15
-10
-5
T
AMIN
- Minimum Ambient Temperature -
°C
0
0·001
-25
0
25
50
75
100 125
T
J
- Junction Temperature -
°C
150
0.95
-40
Figure 2.
Figure 3.
100
NORMALIZED V(BO)
vs
AMBIENT TEMPERATURE
TC3MAL
TC4XAC
2.0
NORMALIZED HOLDING CURRENT
vs
JUNCTION TEMPERATURE
TC4XAD
V
(BO)
Normalized Curren t - A
I - On-State to 25
°C
Value
1.1
Normalized Holding Current
'4125
THRU
'4180
'4072
AND
'4082
1.5
1.0
0.9
0.8
0.7
0.6
0.5
10 '4240
THRU
1.0
'4380
'4240
THRU
'4380
T
25°C
'4072
150°C
AND
'4082
1 -25
-40°C
0.91
0.4
2
13
4
5
7
0
25
50
75
100 6 125 8 9
150
V
T
- On-State Voltage - -V
T
A
- Ambient Temperature
°C
-25
0
25
50
75
100
125
150
T
J
- Junction Temperature -
°C
Figure 4.
NOVEMBER 1997 - REVISED FEBRUARY 2005
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
Figure 5.
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