IS61C5128AL/AS
IS64C5128AL/AS
512K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
HIGH SPEED: (IS61/64C5128AL)
• High-speed access time: 10ns, 12 ns
• Low Active Power: 150 mW (typical)
• Low Standby Power: 10 mW (typical)
CMOS standby
LOW POWER: (IS61/64C5128AS)
• High-speed access time: 25ns
• Low Active Power: 75 mW (typical)
• Low Standby Power: 1 mW (typical)
CMOS standby
• TTL compatible interface levels
• Single 5V ± 10% power supply
• Fully static operation: no clock or refresh
required
• Available in 36-pin SOJ (400-mil), 32-pin
sTSOP-I, 32-pin SOP, 44-pin TSOP-II and 32-
pin TSOP-II packages
• Commercial, Industrial and Automotive tempera-
ture ranges available
• Lead-free available
MARCH 2008
DESCRIPTION
The
ISSI
IS61C5128AL/AS and IS64C5128AL/AS are high-
speed,
4,194,304-bit
static RAMs organized as 524,288
words by 8 bits. They are fabricated using
ISSI
's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields
access times as fast as 12 ns with low power consumption.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be reduced
down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,
CE
and
OE.
The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IS61C5128AL/AS and IS64C5128AL/AS are packaged
in the JEDEC standard 36-pin SOJ (400-mil), 32-pin sTSOP-
I, 32-pin SOP, 44-pin TSOP-II and 32-pin TSOP-II packages
FUNCTIONAL BLOCK DIAGRAM
A0-A18
DECODER
512K X 8
MEMORY ARRAY
V
DD
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE
OE
WE
CONTROL
CIRCUIT
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
03/04/2008
1
IS61C5128AL/AS
TRUTH TABLE
Mode
Not Selected
Output Disabled
Read
Write
WE
X
H
H
L
IS64C5128AL/AS
CE
H
L
L
L
OE
X
H
L
X
I/O0-I/O7
High-Z
High-Z
D
OUT
D
IN
I/O PIN
V
DD
Current
I
SB
1
, I
SB
2
I
CC
1
, I
CC
2
I
CC
1
, I
CC
2
I
CC
1
, I
CC
2
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
STG
P
T
I
OUT
Parameter
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +7.0
–65 to +150
1.5
20
Unit
V
°C
W
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE
(1,2)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
5
7
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz, V
DD
= 5.0V.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
V
OH
V
OL
V
IH
V
IL
I
LI
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
GND
≤
V
IN
≤
V
DD
Com.
Ind.
Auto.
Com.
Ind.
Auto.
Test Conditions
V
DD
= Min., I
OH
= –4.0 mA
V
DD
= Min., I
OL
= 8.0 mA
Min.
2.4
—
2.2
–0.3
–1
–2
–5
–1
–2
–5
Max.
—
0.4
V
DD
+ 0.5
0.8
1
2
5
1
2
5
Unit
V
V
V
V
µA
I
LO
Output Leakage
GND
≤
V
OUT
≤
V
DD
Outputs Disabled
µA
Note:
1. V
IL
= –3.0V for pulse width less than 10 ns.
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
03/04/2008