RF2637
0
Typical Applications
• 3V Basestation Systems
• General Purpose Linear IF Amplifier
• Commercial and Consumer Systems
• Portable Battery-Powered Equipment
RECEIVE AGC AMPLIFIER
Product Description
The RF2637 is a complete AGC amplifier designed for
the receive section of 3V cellular and PCS applications
basestations. It is designed to amplify IF signals while
providing more than 90dB of gain control range. Noise
Figure, IP
3
, and other specifications are designed for bas-
estations. The IC is manufactured on an advanced high
frequency SiGe process, and is packaged in a standard
miniature 8-lead plastic MSOP package.
6° MAX
0° MIN
0.192
+ 0.008
0.012
0.006
+ 0.003
-A-
0.0256
0.118
+ 0.004 sq.
0.034
NOTES:
1. Shaded lead is pin 1.
2. All dimensions are exclusive of
flash, protrusions or burrs.
3. Lead coplanarity: 0.002 with
respect to datum "A".
0.021
+ 0.004
0.006
+ 0.002
Optimum Technology Matching® Applied
Si BJT
Si Bi-CMOS
InGaP/HBT
GaAs HBT
SiGe HBT
GaN HEMT
GaAs MESFET
Si CMOS
SiGe Bi-CMOS
Package Style: MSOP-8
Features
• Supports Basestation Applications
• -55dB to +51dB Gain Control Range @
85MHz
• Single 3V Power Supply
• -2dBm Input IP
3
• 12MHz to 385MHz Operation
IN+ 1
IN- 2
GND 3
GC 4
GAIN
CONTROL
8 VCC1
7 VCC2
6 OUT+
Ordering Information
5 OUT-
RF2637
RF2637 PCBA
Receive AGC Amplifier
Fully Assembled Evaluation Board
Functional Block Diagram
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
Rev A3 040511
10-41
RF2637
Absolute Maximum Ratings
Parameter
Supply Voltage
Control Voltage
Input RF Power
Operating Ambient Temperature
Storage Temperature
Value
-0.5 to +7.0
-0.5 to +5.0
+10
-40 to +85
-40 to +150
Unit
V
DC
V
DC
dBm
°C
°C
Caution!
ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
Parameter
Specification
Min.
Typ.
Max.
Unit
Condition
T=25°C, 85MHz, V
CC
=3.0V, Z
S
=500Ω,
Z
L
=500Ω, 500Ω External Input Terminating
Resistor, 500Ω External Output Terminating
Resistor (Effective Z
S
=333Ω, Effective
Z
L
=250Ω) (See Application Example)
Overall
Frequency Range
Maximum Gain
Minimum Gain
Maximum Gain
Minimum Gain
Gain Slope
Gain Control Voltage Range
Gain Control Input Impedance
Noise Figure
Input IP
3
Stability (Max VSWR)
+40
-65
+35
-68
-46
10:1
12 to 385
+51
-55
+45
-58
57
0 to 2.5
30
5
-40
-2
+65
-40
+55
-48
7.2
MHz
dB
dB
dB
dB
dB/V
V
DC
kΩ
dB
dBm
dBm
V
GC
=2.5V, 85MHz
V
GC
=0.1V, 85MHz
V
GC
=2.5V, 385MHz
V
GC
=0.1V, 385MHz
Note 1
Source impedance of 4.7kΩ
At maximum gain and 85MHz
At +40dB gain, referenced to 500Ω
At minimum gain, referenced to 500Ω
Spurious<-70dBm
CDMA, differential
IF Input
Input Impedance
1
2.7 to 3.4
10
11.5
kΩ
V
mA
mA
°C/W
°C
Power Supply
Voltage
Current Consumption
6
7
15
15
Minimum gain, V
CC
=3.0V
Maximum gain, V
CC
=3.0V
Theta J-Ref 85°C
Ref 85°C
Thermal
Thermal Resistance
150
Maximum Junction Temperature
90
Note 1: Measured between a gain control voltage of 1.0V to 1.5V.
10-42
Rev A3 040511
RF2637
Pin
1
Function
IN+
Description
CDMA balanced input pin. This pin is internally DC-biased and should
be DC-blocked if connected to a device with a DC level other than V
CC
present. A DC to connection to V
CC
is acceptable. For single-ended
input operation, one pin is used as an input and the other CDMA input
is AC-coupled to ground. The balanced input impedance is 1kΩ, while
the single-ended input impedance is 500Ω.
Same as pin 2, except complementary input.
Ground connection. For best performance, keep traces physically short
and connect immediately to ground plane.
Analog gain adjustment for all amplifiers. Valid control ranges are from
0V to 2.5V. Maximum gain is selected with 2.5V. Minimum gain is
selected with 0V. These voltages are only valid for a 4.7kΩ DC source
impedance.
Interface Schematic
BIAS
700
Ω
CDMA+
700
Ω
CDMA-
2
3
4
IN-
GND
GC
See pin 1.
V
CC
12.7 kΩ
23.5 kΩ
15 kΩ
5
OUT-
6
7
OUT+
VCC2
Balanced output pin. This is an open-collector output, designed to
operate into a 250Ω balanced load. The load sets the operating imped-
OUT+
ance, but an external choke or matching inductor to V
CC
must also be
supplied in order to correctly bias this output. This bias inductor is typi-
cally incorporated in the matching network between the output and next
stage. Because this pin is biased to V
CC
, a DC-blocking capacitor must
be used if the next stage’s input has a DC path to ground.
Same as pin 5, except complementary output.
See pin 5.
Supply voltage pin. External bypassing is required. The trace length
between the pin and the bypass capacitors should be minimized. The
ground side of the bypass capacitors should connect immediately to
ground plane.
Same as pin 7.
OUT-
8
VCC1
See pin 7.
Rev A3 040511
10-43
RF2637
Application Schematic
Measurement
Reference Plane
Z
S
=500
Ω
CDMA IF Filter
CDMA+
CDMA-
Z
IN, EFF
=500
Ω
Z
S, EFF
=333
Ω
1
2
Z
IN
=1 kΩ
3
GAIN
4.7 kΩ
4
GAIN
CONTROL
6
R2: 500Ω
5
Z
LOAD,EFF
=250
Ω
C1
L1
V
CC
C2
OUT-
Measurement
Reference Plane
Z
OUT
=500
Ω
8
7
10 nF
V
CC
L1
Z
LOAD
=500Ω
C2
OUT+
R1:
1 kΩ
C1
R1 sets the CDMA balanced input impedance. The effective input impedance is then 500
Ω.
R2 sets the balanced output impedance to 500
Ω.
L1 and C2 serve dual purposes. L1 serves
as an output bias choke, and C2 serves as a series DC block. In addition, the values of L1
and C2 may be chosen to form an impedance matching network of the load impedance is not
500
Ω.
Otherwise, the values of L1 and C1 are chosen to form a parallel-resonant tank circuit
at the IF when the load impedance is 500
Ω.
10 nF
Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
CDMA
J1
SMA
50
Ω µstrip
T1
C3
15 pF
C4
15 pF
L2
390 nH
L1
390 nH
C1
10 nF
C2
10 nF
R1
1 kΩ
1
2
3
4
GAIN
CONTROL
8
7
6
5
L3
390nH
C9
15 pF
L4
390nH
C8
15 pF
C10
10 nF
VCC
OUT
T2
R3
510
Ω
50
Ω µstrip
J2
SMA
GC
P1
P1-1
1
2
P1-3
3
VCC
GND
GC
R2
4.7 kΩ
C5
1 nF
2627400A
VCC
C6
10 nF
C7
10 nF
10-44
Rev A3 040511
RF2637
Evaluation Board Layout
Board Size 2.750" x 2.000"
Board Thickness 0.031”, Board Material FR-4
Rev A3 040511
10-45
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