RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
RM7065A
RM7065A™ Microprocessor with On-
Chip Secondary Cache
Data Sheet
Preliminary
Issue 2, June 2001
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2010145, Issue 2
RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Legal Information
Copyright
© 2001 PMC-Sierra, Inc.
The information is proprietary and confidential to PMC-Sierra, Inc., and for its customers’ internal
use. In any event, you cannot reproduce any part of this document, in any form, without the
express written consent of PMC-Sierra, Inc.
PMC-2010145 (P1)
Disclaimer
None of the information contained in this document constitutes an express or implied warranty by
PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such
information or the fitness, or suitability for a particular purpose, merchantability, performance,
compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any
portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all
representations and warranties of any kind regarding the contents or use of the information,
including, but not limited to, express and implied warranties of accuracy, completeness,
merchantability, fitness for a particular use, or non-infringement.
In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or
consequential damages, including, but not limited to, lost profits, lost business or lost data
resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has
been advised of the possibility of such damage.
Trademarks
RM7000A and Fast Packet Cache are trademarks of PMC-Sierra, Inc.
Patents
The technology discussed is protected by one or more of the following Patents:
U.S. Patent Numbers 5,953,748 5,606,683 5,760,620.
Relevant patent applications and other patents may also exist.
Contacting PMC-Sierra
PMC-Sierra, Inc.
105-8555 Baxter Place Burnaby, BC
Canada V5A 4V7
Tel: (604) 415-6000
Fax: (604) 415-6200
Document Information: document@pmc-sierra.com
Corporate Information: info@pmc-sierra.com
Technical Support: apps@pmc-sierra.com
Web Site: http://www.pmc-sierra.com
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2010145, Issue 2
2
RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Revision History
Issue
No.
2
1
Issue Date
June 2001
April 2001
Details of Change
Changed IP references to INT, page 34. Changed W7 pin name to SysClk.
Applied PMC-Sierra template to existing MPD (QED) preliminary FrameMaker
document.
Updated Sections 4.33, 4.34, 4.38, 9, and 12. In the Pinout Table, changed all
references from IP to Int.
Changed QED references to PMC-Sierra or MIPS.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2010145, Issue 2
3
RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Document Conventions
The following conventions are used in this datasheet:
•
•
•
All signal, pin, and bus names described in the text, such as
ExtRqst*,
are in boldface
typeface.
All bit and field names described in the text, such as
Interrupt Mask,
are in an italic-bold
typeface.
All instruction names, such as
MFHI,
are in san serif typeface.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2010145, Issue 2
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RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Table of Contents
1
2
3
4
Features ..................................................................................................................................9
Block Diagram .......................................................................................................................10
Description ............................................................................................................................11
Hardware Overview ...............................................................................................................12
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
CPU Registers .............................................................................................................12
Superscalar Dispatch ...................................................................................................12
Pipeline ........................................................................................................................13
Integer Unit ..................................................................................................................14
ALU ..............................................................................................................................15
Integer Multiply/Divide ..................................................................................................15
Floating-Point Coprocessor ..........................................................................................16
Floating-Point Unit .......................................................................................................16
Floating-Point General Register File ............................................................................17
4.10 System Control Coprocessor (CP0) .............................................................................18
4.11 System Control Coprocessor Registers .......................................................................18
4.12 Virtual to Physical Address Mapping ............................................................................19
4.13 Joint TLB ......................................................................................................................20
4.14 Instruction TLB .............................................................................................................21
4.15 Data TLB ......................................................................................................................21
4.16 Cache Memory .............................................................................................................22
4.17 Instruction Cache .........................................................................................................22
4.18 Data Cache ..................................................................................................................22
4.19 Secondary Cache ........................................................................................................24
4.20 Secondary Caching Protocols ......................................................................................24
4.21 Cache Locking .............................................................................................................25
4.22 Cache Management .....................................................................................................26
4.23 Primary Write Buffer .....................................................................................................26
4.24 System Interface ..........................................................................................................26
4.25 System Address/Data Bus ...........................................................................................27
4.26 System Command Bus ................................................................................................27
4.27 Handshake Signals ......................................................................................................28
4.28 System Interface Operation .........................................................................................28
4.29 Data Prefetch ...............................................................................................................30
4.30 Enhanced Write Modes ................................................................................................31
4.31 External Requests ........................................................................................................31
4.32 Test/Breakpoint Registers ............................................................................................31
4.33 Performance Counters .................................................................................................32
4.34 Interrupt Handling ........................................................................................................34
4.35 Standby Mode ..............................................................................................................36
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2010145, Issue 2
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