HT82V842
CCD CDS/PGA/10b-20M-ADC
Features
·
Operating voltage: 2.7V~3.6V
·
Low power consumption: 70mW (Typ.)
·
Power down mode: less than 30mW
·
Accepts a direct signal input to ADC or PGA at 1.0
·
Independent ADC input conversion clock and data
output clock
·
Independent CDS and PGA gain control
-
CDS:
-1.94/0/6/12dB
-
PGA: 0~24dB
·
Wide gain range:
-1.94~36dB
·
High speed sample and hold circuit: pulse width 11ns
V
PP
(Typ.)
·
CCD signal input level: 1.1 V
P-P
(Max.)
·
10-bit ADC (up to 20MHz)
·
Black level neutralizer, target setting: 16~127LSB
·
Built-in serial interface
-
DNL:
±0.6
LSB (Typ.)
(Min.)
·
48-pin LQFP package
General Description
The HT82V842 is a CMOS single-chip signal process-
ing device for CCD area sensors. It consists of a clamp
circuit, Correlated Double Sampler (CDS), Programma-
ble Gain Amplifier (PGA), reference voltage generator,
black level detection circuit, 20MHz 10-bit A/D converter
(ADC), timing generator for internally required pulses,
serial interface for internal function control and PGA
gain control.
Block Diagram
O B P C C D C L P A D C L P
A D C K
B L K
C L P C A P
C S S C K S D A T A
M O N O U T
T im in g
G e n e ra to r
S e r ia l
R e g is te r
B a n d G a p
C ir c u it
V R P
V C O M
V R N
D C C la m p
C C D C L P
R E F IN
C C D IN
C C D
A D IN
O B C A P
O B P
D A C
C o m p a re
B la c k L e v e l
R e g is te r
A D C L P
C D S
P G A
R o u g h
P G A
F in e
0 ~ 6 d B
(0 .0 4 7 d B /S te p )
1 0 - B it
A D C
D O 0 ~ D O 9
S /H
-1 .9 4 /0 /6 /1 2 d B
0 /6 /1 2 /1 8 d B
V
D D
V
S S
R E S E T S T B Y S H R S H D
O U T C K
Rev. 1.00
1
July 15, 2004
HT82V842
Pin Assignment
D O 0
D O 1
D O 2
D O 3
D O 4
V S S
V D D
D O 5
D O 6
D O 7
D O 8
D O 9
N C
V D D
N C
V R N
V R P
V D D
V D D
V S S
V S S
V C O M
C C D IN
R E F IN
2
3
4
5
6
7
8
9
1 0
1 1
1
4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7
3 6
3 5
3 4
3 3
H T 8 2 V 8 4 2
4 8 L Q F P -A
3 2
3 1
3 0
2 9
2 8
2 7
2 6
1 2
2 5
1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4
S H
S H
A D
N C
V S
V D
N C
N C
M O
O B
A D
C L
N O U T
C A P
IN
P C A P
S
D
C K
R
D
O U
R E
V D
V S
S T
C S
S D
S C
O B
C C
B L
A D
K
S
B Y
A T A
K
P
D C L P
D
T C K
S E T
C L P
Pin Description
Pin No.
1, 3, 17~18, 21
2, 6~7, 19, 34, 43
4
5
8~9, 20, 33, 42
10
11
12
13
14
15
16
22
23
24
25
26
27
28
29
30
31
32
35
36
37~41, 44~48
Pin Name
NC
VDD
VRN
VRP
VSS
VCOM
CCDIN
REFIN
CLPCAP
ADIN
OBCAP
MONOUT
ADCK
SHR
SHD
ADCLP
BLK
CCDCLP
OBP
SCK
SDATA
CS
STBY
RESET
OUTCK
DO0~DO9
I/O
¾
¾
O
O
¾
O
I
I
O
I
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
O
No connection
Positive power supply for analog circuit
Negative reference voltage for internal ADC
Connect to V
SS
via 0.1mF
Positive reference voltage for internal ADC
Connect to V
SS
via 0.1mF
Negative power supply for analog circuit
Common reference voltage for internal ADC
CDS circuit data input
CDS circuit reference input
Clamp level output
Connect to V
SS
via 0.1mF
ADIN signal input
Black level integration voltage
Connect to V
SS
via 0.1mF~1mF (by applications)
Monitor output of CDS or PGA
ADC sampling clock input
Reference sampling pulse input
Data sampling pulse input
Pulse input for ADIN clamp and black calibration control
Blanking pulse input
Clamp control input
Black level period pulse input
Serial clock input
Serial data input
Serial port chip selection (Active at low)
Power down control (Active low)
Reset signal (Active low)
Clock source for ADC output
Digital output from ADC
Description
Rev. 1.00
2
July 15, 2004
HT82V842
Absolute Maximum Ratings
Supply Voltage .........................GND-0.3V to GND+6V
Input Voltage .............................V
SS
-0.3V
to V
DD
+0.3V
Storage Temperature ...........................-55°C to 150°C
Operating Temperature ..........................-20°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under
²Absolute
Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
D.C. Characteristics
Symbol
V
IH
V
IL
I
IH
I
IL
I
MD
I
MA
I
SS
V
CCDIN
Analog Input Range
V
ADIN
V
CLPCAP
t
BLKCAL
V
BLKCAL
G (0)
G (1)
G (2)
G (3)
Gmin
Gmax
Gstep
ER
PA
RES
DNL
SN
SND
V
COM
V
RP
V
RN
Clamp Voltage
Black Calibration Time
Maximum Calibration Offset Voltage
CDS Gain (Set 0 dB)
CDS Gain (Set 6.02 dB)
CDS Gain (Set 12.04 dB)
CDS Gain (Set
-1.94
dB)
PGA Gain (Minimum Gain)
PGA Gain (Maximum Gain)
PGA Gain (Gain Step)
Total (CDS+PGA) Gain Monotony
Resolution
Differential Nonlinearity
S/N
S/(N+D)
ADC Common Voltage
V
RP
Voltage (Positive)
V
RN
Voltage (Negative)
3V
3V
3V
3V
3V
3V
3V
3V
3V
3V
Relative gain
3V
3V
3V
3V
3V
3V
3V
3V
3V
¾
¾
f
S
=20MHz
¾
¾
¾
¾
¾
0
¾
¾
¾
¾
¾
1.25
1.55
1.05
0.047
¾
¾
±0.6
58
56
1.4
1.65
1.15
0.094
±4
10
±1.0
¾
¾
1.55
1.75
1.25
Absolute gain
Relative gain
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Operation Current at Monitor Disable
Supply Current at Monitor Active
Power Down Current
Test Conditions
V
DD
3V
3V
3V
3V
3V
3V
3V
3V
Conditions
¾
¾
V
IL
=0V
V
IH
=3.0V
f
S
=20MHz
f
S
=20MHz
¾
CCDIN input,
f
IN
=1MHz
ADIN input,
f
IN
=1MHz
¾
¾
¾
Absolute gain
Min.
0.7V
DD
0
¾
¾
¾
¾
¾
¾
¾
1.5
¾
¾
-2
5.52
11.54
-2.44
-1.2
22.906
Typ.
¾
¾
¾
¾
23
26
¾
1.1
1.0
1.7
¾
±200
-1
6.02
12.04
-1.94
-0.2
23.906
Max.
V
DD
0.3V
DD
200
1
¾
¾
10
¾
¾
1.9
200
¾
0
6.52
12.04
-1.44
0.8
24.906
Ta=25°C
Unit
V
V
mA
mA
mA
mA
mA
V
P-P
V
P-P
V
Pixel
mV
dB
dB
dB
dB
dB
dB
dB
LSB
Bits
LSB
dB
dB
V
V
V
Rev. 1.00
3
July 15, 2004
HT82V842
Symbol
Parameter
Test Conditions
V
DD
3V
3V
Conditions
¾
¾
Min.
16
1
¾
Typ.
¾
¾
1
Max.
127
127
¾
Unit
LSB
LSB
LSB
C
CAL
ST
CAL
Note:
ADC Output Black Level Calibration Code
Calibration Code Resolution
Black calibration period is specified when C
CAL
is from 16 to 127LSB. Although black level codes of 1 to 15
could be set, t
BLKCAL
is not guaranteed for these codes.
V
SS
=0V, Ta=25°C
Test Conditions
V
DD
3.0V
3.0V
3.0V
3.0V
3.0V
3.0V
3.0V
3.0V
3.0V
3.0V
3.0V
3.0V
3.0V
3.0V
3.0V
3.0V
3.0V
Conditions
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
Min.
0.5
50
¾
¾
23
23
11
11
¾
¾
2
5
1
10
10
0
10
¾
¾
¾
Typ.
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
20
20
6
Max.
20
¾
2
2
¾
¾
¾
¾
4
4
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
A.C. Characteristics
Symbol
f
S
t
CYC
t
R
t
F
t
L
t
H
t
WR
t
WD
t
DR
t
DD
t
PSUP
t
HOLD
t
SP
t
SUPE
t
HOLDE
t
SUPOC
t
HOLDOC
t
DLD
t
DLE
t
DL
Parameter
Conversion Frequency
Clock Cycle Time
Clock Rising Time
Clock Falling Time
Clock Low Period
Clock High Period
SHR Pulse Width
SHD Pulse Width
SHR Sampling Aperture
SHD Sampling Aperture
Data Pulse Setup
Data Pulse Hold
Sampling Pulse Non-overlay
Enable Pulse Setup
Enable Pulse Hold
OUTCK Setup
OUTCK Hold
3-state Disable Delay
3-state Disable Delay
ADC Output Data Delay
3.0V Active
®
High-Z
3.0V High-Z® Active
3.0V
¾
Rev. 1.00
4
July 15, 2004
HT82V842
Functional Description
CDS (Correlated Double Sampling) Circuit
Connect the CCDIN pin to the CCD sensor thru a capac-
itor. Connect also the REFIN pin to V
SS
thru a capacitor.
The CDS circuit holds the pre-charge voltage of the
CCD at SHR pulse and do sampling of the CCD pixel
data at SHD pulse. Correlated noise is removed by sub-
tracting the pre-charge voltage from the pixel data level.
CDS could choose a gain setting from 0, 6.02, 12 or
-1.94dB
(Mode 3, register D4 and D5 bits). A CDS gain
is controlled by PGA gain. It is recommended to in-
crease the CDS gain then increase the PGA gain to re-
duce the noise level.
Clamp Circuits
·
DC clamp
¨
Clamp target (Mode 2 register D5 and D4), input
signals (REFIN and CCDIN) to be clamped are
selectable. The clamp function can be turned off.
Black Level Cancel Circuit
The purpose of a black level cancel circuit is to control
the DC level of the PGA input. The ADC output code at
an optical black period may correspond to the black
level code set up by the register. A black level code of (1
to) 16 to 127 LSB is available (the default is 64 LSB).
While the OBP pin is active a black level cancel loop is
established. In the loop, a comparison is made between
the ADC output code and the black level code, the result
controls the voltage of the OBCAP capacitor. Hence, the
OBCAP voltage settles gradually and the signal level of
the optical black period corresponds to the established
value.
The following conditions will reset the OBCAP capaci-
tor:
·
Set the black level reset register to
²1²
(Mode 1 regis-
The DC level of the CCDIN/REFIN input is fixed by an
internal DC clamp circuit. The DC level of the
C-coupled CCD signal at the CDS input is set to
CLPCAP by the internal DC clamp circuit. The clamp
switches are usually turned on at the black level cali-
bration period. The CLPCAP pin connects to V
SS
thru
a 0.1mF capacitor.
·
ADIN signal clamp
ter D1=1).
·
Set the RESET pin to low
·
Power down by STBY pin or register control
Clamp operation can also be used for the ADIN path.
The clamp voltage is different from the CCDIN/REFIN
signal and it could be turned off by register setting. At
²ADIN
signal to ADC² mode, the ADCLP signal con-
trols the
²clamp
circuit². Black level calibration circuit
is also controlled by ADCLP at
²ADIN
signal to PGA²
mode.
·
Clamp control
¨
The DC clamping (CCDCLP) is allowed while the OBP
pin is low. The black level cancellation is available at
²ADIN
signal to PGA² mode. The black level cancella-
tion is available at the ADCLP period in this mode. The
clamping function and black level canceling function are
done simultaneously.
Clamp current (Mode 2 register D7). Charge current
can select normal or fast clamp.
C C D
O B
A D C K
E ffe c tiv e P ix e l
B la n k in g
B L K
O B P
C C D C L P
O U T C K
D O
0
~ D O
9
D a ta O u tp u t
B la c k C o d e
Rev. 1.00
5
July 15, 2004
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