electromagnetic interference (EMI) at the clock source
which provides system wide reduction of EMI of all clock
dependent signals. The P2010A allows significant system
cost savings by reducing the number of circuit board layers
and shielding that are traditionally required to pass EMI
regulations.
The P2010A uses the most efficient and optimized
modulation
profile
approved
by
the
FCC
and
is
implemented in a proprietary all-digital method.
The P2010A modulates the output of a single PLL in order
to “spread” the bandwidth of a synthesized clock and, more
importantly,
decreases
the
peak
amplitudes
of
its
harmonics. This results in significantly lower system EMI
compared to the typical narrow band signal produced by
oscillators and most frequency generators. Lowering EMI
by increasing a signal’s bandwidth is called “spread
spectrum clock generation”.
Product Description
The P2010A is a selectable spread spectrum frequency
modulator designed specifically for PC peripheral and
embedded controller markets. The P2010A reduces
Applications
The P2010A is targeted towards the embedded controller
market and PC peripheral markets including scanners,
facsimile, MFP’s, printers, PDA, IA, and GPS devices
.
Block Diagram
FS0
SR1
SSON
VDD
Modulation
XIN
XOUT
Crystal
Oscillator
Frequency
Divider
Feedback
Divider
Phase
Detector
Loop
Filter
VCO
PLL
Output
Divider
ModOUT
VSS
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
•
Tel: 408-879-9077
•
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
November 2006
rev 0.2
Pin Configuration
1
XIN/CLK 1
2
XOUT 2
FS0 33
4
VSS 4
8 VDD
8
7 SR0
7
6 ModOUT
6
5
5
SSON
P2010A
P2040C
P2010A
Pin Description
Pin#
1
2
3
4
5
6
7
8
Pin Name
XIN/CLK
XOUT
FS0
VSS
SSON
ModOUT
SR0
VDD
Type
I
I
I
P
I
O
I
P
Description
Connect to crystal or externally generated clock signal.
Connect to crystal. No connect if externally generated clock signal is used.
Digital logic input used to select Input Frequency Range (see Table 1).
This pin has an internal pull-up resistor.
Ground Connection. Connect to system ground.
Digital logic input used to enable Spread Spectrum function (Active Low).
Spectrum function enable when low. This pin has an internal pull-low resistor.
Spread Spectrum Clock Output.
Digital logic input used to select Spreading Range (see Table 1).
This pin has an internal pull-up resistor.
Connect to +3.3V or +5.0V
Spread
Table 1 - Spread Range Selection
FS0
1
1
0
0
SR0
0
1
0
1
Spreading Range
+/- 1.50%
+/- 2.50%
+/- 1.25%
+/- 2.00%
Input Frequency
10MHz to 20MHz
10MHz to 20MHz
20MHz to 35MHz
20MHz to 35MHz
Modulation rate
(Fin/10)*20.83KHz
(Fin/10)*20.83KHz
(Fin/10)*20.83KHz
(Fin/10)*20.83KHz
Low Frequency EMI Reduction IC
Notice: The information in this document is subject to change without notice.
2 of 8
November 2006
rev 0.2
Spread Spectrum Selection
P2010A
Table 1 illustrates the possible spread spectrum options. The optimal setting should minimize system EMI to the fullest
without affecting system performance. The spreading is described as a percentage deviation of the center frequency
(Note: the center frequency is the frequency of the external reference input on XIN/CLK, Pin 1).
Example of a typical printer or scanner application that operates on a clock frequency of 16MHz:
A spreading selection of FS0=1 and SR0=1 provides a percentage deviation of +/-2.50%* (see Table 1) of Center
Frequency. This results in the frequency on ModOUT being swept from 16.40MHz to 15.60MHz at a modulation rate of
33.33KHz (see Table 1). This particular example (see Figure below) given here is a common EMI reduction method for
scanner, printer or embedded applications and has already been adopted by most of the leading manufacturers.
Note: Spreading range selection varies from different system manufacturers and their designs.
P2010A Application Schematic for Flat-Bed Scanner
VDD
16MHz Crystal Input
1 XIN/CLK
2 XOUT
3 FS0
4 VSS
VDD 8
SR0 7
ModOUT 6
SSON 5
P2010A
0.1µF
Connected to CLK input pin of the system
Low Frequency EMI Reduction IC
Notice: The information in this document is subject to change without notice.
3 of 8
November 2006
rev 0.2
Absolute Maximum Ratings
Symbol
V
DD
, V
IN
T
STG
T
A
T
s
T
J
T
DV
Storage temperature
Operating temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
P2010A
Parameter
Voltage on any pin with respect to Ground
Rating
-0.5 to +7
-65 to +125
-40 to+85
260
150
2
Unit
V
°C
°C
°C
°C
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
DC Electrical Characteristics
Symbol
V
IL
V
IH
I
IL
I
IH
I
XOL
I
XOH
V
OL
V
OH
I
DD
I
CC
VDD
t
ON
Z
OUT
Input Low Voltage
Input High Voltage
Input Low Current (pull-up resistor on inputs SR0, FS0)
Input High Current (pull-down resistor on input SSON)
XOUT output low current (at 0.4V, VDD = 3.3V)
XOUT output high current (at 2.5V, VDD = 3.3V)
Output Low Voltage (VDD=3.3V, I
OL
= 20mA)
Output High Voltage (VDD=3.3V, I
OH
= 20mA)
Static Supply Current
Dynamic Supply Current (3.3V and 15pF loading)
Operating Voltage
Power Up Time (First locked clock cycle after power up)
Clock Output Impedance
Parameter
Min
GND
2.0
-
-
-
-
-
2.5
-
4
2.7
Typ
-
-
-
-
3
3
-
-
0.6
6
3.3
0.18
50
Max
0.8
VDD + 0.3
-35
35
-
-
0.4
-
-
8
5.5
Unit
V
V
µA
µA
mA
mA
V
V
mA
mA
V
mS
Ω
AC Electrical Characteristics
Symbol
f
IN
t
LH
*
t
HL
*
t
JC
t
D
Input Frequency
Output rise time
(Measured at 0.8V to 2.0V)
Output fall time
(Measured at 2.0V to 0.8V)
Jitter (Cycle to cycle)
Output duty cycle
Parameter
Min
10
0.7
0.6
-
45
Typ
20
0.9
0.8
-
50
Max
35
1.1
1.0
360
55
Unit
MHz
nS
nS
pS
%
*t
LH
and t
HL
are measured into a capacitive load of 15pF
Low Frequency EMI Reduction IC
Notice: The information in this document is subject to change without notice.
4 of 8
November 2006
rev 0.2
Package Information
8-lead (150-mil) SOIC Package
P2010A
E
H
D
A2
A
θ
e
B
A
1
C
L
D
Dimensions
Symbol
Min
A1
A
A2
B
C
D
E
e
H
L
θ
Inches
Max
0.010
0.069
0.059
0.020
0.010
0.004
0.053
0.049
0.012
0.007
Millimeters
Min
Max
0.10
1.35
1.25
0.31
0.18
4.90 BSC
3.91 BSC
1.27 BSC
6.00 BSC
0.41
0°
1.27
8°
0.25
1.75
1.50
0.51
0.25
0.193 BSC
0.154 BSC
0.050 BSC
0.236 BSC
0.016
0°
0.050
8°
Low Frequency EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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