This X24C01A device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
1K
ICmic
TM
IC MICROSYSTEMS
X24C01A
Serial E PROM
2
DESCRIPTION
128 x 8 Bit
FEATURES
•
2.7V to 5.5V Power Supply
•
Low Power CMOS
—Active Current Less Than 1 mA
—Standby Current Less Than 50 µA
•
Internally Organized 128 x 8
The X24C01A is a CMOS 1024 bit serial E PROM,
internally organized 128 x 8. The X24C01A features a
serial interface and software protocol allowing operation on a
simple two wire bus. Three address inputs allow up
2
to eight devices to share a common two wire bus.
Xicor E PROMs are designed and tested for applications
requiring extended endurance. Inherent data retention
is greater than 100 years. Available in an eight pin DIP and
SOIC package.
2
•
Self Timed Write Cycle
—Typical Write Cycle Time of 5 ms
•
2 Wire Serial Interface
—Bidirectional Data Transfer Protocol
•
Four Byte Page Write Operation
—Minimizes Total Write Time Per Byte
•
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
•
New Hardwire – Write Control Function
FUNCTIONAL DIAGRAM
(8) V
CC
(4) V
SS
(7) WC
START CYCLE
(5) SDA
START
STOP
H.V. GENERATION
TIMING
& CONTROL
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER
(6) SCL
(3) A2
(2) A1
(1) A0
+COMPARATOR
LOAD
INC
XDEC
E PROM
32x32
2
WORD
ADDRESS
COUNTER
R/W
YDEC
8
CK
PIN
DATA REGISTER
D
OUT
D
OUT
ACK
3841 FHD F01
© Xicor, 1991 Patents Pending
3841-1
1
Characteristics subject to change without notice
X24C01A
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out
of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open
collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Guide-
lines for Calculating Typical Values of Bus Pull-Up
Resistors graph.
Address (A
0
, A
1
, A
2
)
The address inputs are used to set the least significant
three bits of the seven bit slave address. These inputs
can be static or actively driven. If used statically they must
be tied to V
SS
or V
CC
as appropriate. If actively
A
0
A
1
A
2
V
SS
PIN CONFIGURATION
DIP/SOIC
1
2
3
4
X24C01A
8
7
6
5
V
CC
WC
SCL
SDA
3841 FHD F02
PIN NAMES
Symbol
A
0
–A
2
SDA
SCL
WC
V
SS
V
CC
Description
Address Inputs
Serial Data
Serial Clock
Write Control
Ground
+5V
3841 PGM T01
driven, they must be driven to V
SS
or to V
CC
.
WRITE CONTROL (WC)
The Write Control input controls the ability to write to the
device. When WC is LOW (tied to V
SS
) the X24C01A will
be enabled to perform write operations. When WC is HIGH
(tied to V
CC
) the internal high voltage circuitry will
be disabled and all writes will be disabled.
DEVICE OPERATION
The X24C01A supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master will always initiate data transfers and provide the
clock for both transmit and receive operations.
Therefore, the X24C01A will be considered a slave in
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are re-
served for indicating start and stop conditions. Refer to
Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24C01A continuously monitors the SDA and
SCL lines for the start condition and will not respond
to any command until this condition has been met.
all applications.
2
X24C01A
Figure 1. Data Validity
SCL
SDA
DATA STABLE
DATA
CHANGE
3841 FHD F05
Figure 2. Definition of Start and Stop
SCL
SDA
START BIT
STOP BIT
3841 FHD F06
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH.
The stop condition is also used by the X24C01A to place
the device into the standby power mode after a
The X24C01A will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write operation have been selected,
the X24C01A will respond with an acknowledge
after the receipt of each subsequent eight bit word.
In the read mode the X24C01A will transmit eight bits of data,
release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the X24C01A
will continue to transmit data. If an acknowledge is not
detected, the X24C01A will terminate further data trans-
missions. The master must then issue a stop condition to
return the X24C01A to the standby power mode and
read sequence. A stop condition can only be issued after the
transmitting device has released the bus.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device will
release the bus after transmitting eight bits. During the ninth
clock cycle the receiver will pull the SDA line LOW
to acknowledge that it received the eight bits of data.
Refer to Figure 3.
place the device into a known state.
Figure 3. Acknowledge Response From Receiver
SCL FROM
MASTER
1
8
9
DATA
OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
3841 FHD F07
3
X24C01A
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type
identifier (see Figure 4). For the X24C01A this is fixed as
Following the start condition, the X24C01A monitors the
SDA bus comparing the slave address being transmitted
with its slave address (device type and state of A
0
,
A
2
inputs). Upon a correct compare the X24C01A
A
1
and
1010[B].
Figure 4. Slave Address
DEVICE TYPE
IDENTIFIER
outputs an acknowledge on the SDA line. Depending on the
state of the R/W bit, the X24C01A will execute a read
or write operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24C01A requires a second
address field. This address field is the word address,
comprised of eight bits, providing access to any one of the
128 words of memory. Note: the most significant bit
1
0
1
0
A2
A1
A0
R/W
DEVICE
ADDRESS
3841 FHD F08
is a don’t care. Upon receipt of the word address the
X24C01A responds with an acknowledge, and awaits
the next eight bits of data, again responding with an
acknowledge. The master then terminates the transfer
by generating a stop condition, at which time the X24C01A
begins the internal write cycle to the nonvolatile memory.
The next three significant bits address a particular
device. A system could have up to eight X24C01A
devices on the bus (see Figure 10). The eight addresses are
defined by the state of the A
0
, A
1
and A
2
inputs.
The last bit of the slave address defines the operation to be
performed. When set to one a read operation is
While the internal write cycle is in progress the X24C01A
inputs are disabled, and the device will not respond to
any requests from the master. Refer to Figure 5 for the
address, acknowledge and data transfer sequence.
selected, when set to zero a write operation is selected.
Figure 5. Byte Write
S
T
BUS ACTIVITY:
MASTER
A
R
SLAVE
ADDRESS
WORD
ADDRESS
DATA
S
T
O
P
T
S
A
C
A
C
A
C
SDA LINE
BUS ACTIVITY:
X24C01A
P
K
K
K
3841 FHD F09
Figure 6. Page Write
S
T
BUS ACTIVITY:
MASTER
A
R
SLAVE
ADDRESS
WORD ADDRESS n
DATA n
DATA n–1
DATA n+3
S
T
O
P
T
S
A
C
A
C
A
C
A
C
A
C
SDA LINE
BUS ACTIVITY:
X24C01A
P
K
K
K
K
K
3841 FHD F10
NOTE: In this example n = xxxx 0000 (B); x = 1 or 0
4
X24C01A
Flow 1. ACK Polling Sequence
WRITE OPERATION
COMPLETED
Page Write
The X24C01A is capable of an four byte page write
operation. It is initiated in the same manner as the byte
write operation, but instead of terminating the write cycle after
the first data word is transferred, the master can
transmit up to three more words. After the receipt of each word,
the X24C01A will respond with an acknowledge.
After the receipt of each word, the two low order address bits
are internally incremented by one. The high order
five bits of the address remain constant. If the master should
transmit more than four words prior to generating
ENTER ACK POLLING
ISSUE
START
the stop condition, the address counter will “roll over” and
the previously written data will be overwritten. As
with the byte write operation, all inputs are disabled until
completion of the internal write cycle. Refer to Figure 6
ISSUE SLAVE
ADDRESS AND R/W = 0
ISSUE STOP
for the address, acknowledge and data transfer
sequence.
Acknowledge Polling
The disabling of the inputs, during the internal write
operation, can be used to take advantage of the typical
5 ms write cycle time. Once the stop condition is issued to
indicate the end of the host’s write operation the
X24C01A initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the
start condition followed by the slave address for a write
operation. If the X24C01A is still busy with the write
operation no ACK will be returned. If the X24C01A has
completed the write operation an ACK will be returned
and the master can then proceed with the next read or write
operation (See Flow 1).
ACK
RETURNED?
NO
YES
NEXT
OPERATION
NO
A WRITE?
YES
ISSUE STOP
ISSUE BYTE
ADDRESS
PROCEED
PROCEED
READ OPERATIONS
Read operations are initiated in the same manner as write
operations with the exception that the R/W bit of the
slave address is set to a one. There are three basic read
operations: current address read, random read and
3841 FHD F11
sequential read.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition
during the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a stop condition.
5
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