W3H32M64E-XSBX
256MB – 32M x 64 DDR2 SDRAM 208 PBGA Multi-Chip Package
FEATURES
Data rate = 667, 533, 400 Mb/s
Package:
• 208 Plastic Ball Grid Array (PBGA), 16 x 20mm
• 1.0mm pitch
Supply Voltage = 1.8V ± 0.1V
Differential data strobe (DQS, DQS#) per byte
Internal, pipelined, double data rate architecture
4-bit prefetch architecture
DLL for alignment of DQ and DQS transitions with clock
signal
Four internal banks for concurrent operation
(Per DDR2 SDRAM Die)
Programmable Burst lengths: 4 or 8
Auto Refresh and Self Refresh Modes
On Die Termination (ODT)
Adjustable data – output drive strength
Programmable CAS latency: 3, 4 or 5
Posted CAS additive latency: 0, 1, 2, 3 or 4
Write latency = Read latency - 1* t
CK
Commercial, Industrial and Military Temperature Ranges
Organized as 32M x 64, user configurable as 2 x 32M x 32
Weight: W3H32M64E-XSBX - 2.5 grams typical
BENEFITS
62% Space savings vs. FBGA
Reduced part count
42% I/O reduction vs FBGA
Reduced trace lengths for lower parasitic capacitance
Suitable for hi-reliability applications
Upgradeable to 64M x 64 density (contact factory for
information)
TYPICAL APPLICATION
RAM
Host
FPGA/
Processor
DDR2/DDR3
W3X128M72-XBI
SSD (SLC)
MSM32/MSM64 (SATA BGA)
)
W7N16GVHxxBI (PATA BGA)
)
M400/M100/M50 (SATA, 2.5in)
n)
)
FIGURE 1 – DENSITY COMPARISONS
CSP Approach (mm)
11.0
11.0
11.0
11.0
W3H32M64E-XSBX
20
19.0
90
FBGA
90
FBGA
90
FBGA
90
FBGA
W3H32M64E-XSBX
16
S
A
V
I
N
G
S
62%
42%
Area
I/O Count
4 x 209mm
2
= 836mm
2
4 x 90 balls = 360 balls
320mm
2
208 Balls
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2011
Rev. 14
© 2011 Microsemi Corporation. All rights reserved.
1
Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
www.microsemi.com/pmgp
W3H32M64E-XSBX
TABLE 1 – BALL DESCRIPTIONS
Symbol
ODT
CK, CK#
Type
Input
Input
Description
On-Die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only
applied to each of the following balls: DQ0–DQ3, LDM, UDM, LDQS, LDQS#, UDQS, and UDQS#. The ODT input will be ignored if
disabled via the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge
of CK and negative edge of CK#. Output data (DQS and DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. The
specific circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides
PRECHARGE power-down mode and SELF-REFRESH action (all banks idle), or ACTIVE power-down (row active in any bank). CKE
is synchronous for power-down entry, Power-down exit, output disable, and for self refresh entry. CKE is asynchronous for self refresh
exit. Input buffers (excluding CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are disabled during
self refresh. CKE is an SSTL_18 input but will detect a LVCMO SLOW level once V
CC
is applied during
fi
rst power-up. After V
REF
has
become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For
proper SELF-REFRESH operation, V
REF
must be maintained.
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when
CS# is registered HIGH.
Command inputs: RAS#, CAS#, WE# (along with CS#) define the command being entered.
Input data mask: DM is an input mask signal for write data. Input data is masked when DM is concurrently sampled HIGH during a
WRITE access. DM is sampled on both edges of DQS. Although DM balls are input-only, the DM loading is designed to match that of
DQ and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is DM for upper byte DQ8–DQ15, of each of IC1-4
Bank address inputs: BA0–BA1 define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0–
BA1 define which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command.
Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA1–BA0) or all banks (A10
HIGH) The address inputs also provide the op-code during a LOAD MODE command.
Data input/output: Bidirectional data bus
Data strobe for upper byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read
data, center-aligned with write data. UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE
command.
Data strobe for lower byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read
data, center-aligned with write data. UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE
command.
Power Supply: 1.8V ±0.1V
Power Supply: I/O; V
CCQ
is common to V
CC
SSTL_18 reference voltage.
Ground
No connect: These balls should be left unconnected.
Future use
CKEA, CKEB
Input
CSA#, CSB#
RASA#, CASA#,
WEA#
RASB#, CASB#,
WEB#
LDM, UDM
BA0–BA1
Input
Input
Input
Input
A0-A12
DQ0-63
UDQS, UDQS#
Input
I/O
I/O
LDQS, LDQS#
V
CC
V
CCQ
V
REF
V
SS
NC
DNU
I/O
Supply
Supply
Supply
Supply
-
-
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2011
Rev. 14
© 2011 Microsemi Corporation. All rights reserved.
4
Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
www.microsemi.com/pmgp
W3H32M64E-XSBX
DESCRIPTION
The 2Gb DDR2 SDRAM is a high-speed CMOS, dynamic random-
access memory containing 2,147,483,648 bits. Each of the four
chips in the MCP are internally configured as 4-bank DRAM. The
block diagram of the device is shown in Figure 2. Ball assignments
and are shown in Figure 3.
The 2Gb DDR2 SDRAM uses a double-data-rate architecture to
achieve high-speed operation. The double data rate architecture is
essentially a 4n-prefetch architecture, with an interface designed
to transfer two data words per clock cycle at the I/O balls. A single
read or write access for the 2Gb DDR2 SDRAM effectively consists
of a single 4n-bit-wide, one-clock-cycle data transfer at the internal
DRAM core and four corresponding
n-bit-wide,
one-half-clock-cycle
data transfers at the I/O balls.
A bidirectional data strobe (DQS, DQS#) is transmitted externally,
along with data, for use in data capture at the receiver. DQS is a
strobe transmitted by the DDR2 SDRAM during READs and by
the memory controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for WRITEs. There
are strobes, one for the lower byte (LDQS, LDQS#) and one for
the upper byte (UDQS, UDQS#).
The 2Gb DDR2 SDRAM operates from a differential clock (CK and
CK#); the crossing of CK going HIGH and CK# going LOW will
be referred to as the positive edge of CK. Commands (address
and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR2 SDRAM are burst oriented;
accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin
with the registration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits registered
coincident with the ACTIVE command are used to select the bank
and row to be accessed. The address bits registered coincident
with the READ or WRITE command are used to select the bank
and the starting column location for the burst access.
The DDR2 SDRAM provides for programmable read or write
burst lengths of four or eight locations. DDR2 SDRAM supports
interrupting a burst read of eight with another read, or a burst
write of eight with another write. An auto precharge function may
be enabled to provide a self-timed row precharge that is initiated
at the end of the burst access.
As with standard DDR SDRAMs, the pipelined, multibank
architecture of DDR2 SDRAMs allows for concurrent operation,
thereby providing high, effective bandwidth by hiding row precharge
and activation time.
A self refresh mode is provided, along with a power-saving power-
down mode.
All inputs are compatible with the JEDEC standard for SSTL_18.
All full drive-strength outputs are SSTL_18-compatible.
•
Throughout the data sheet, the various
fi
gures and text refer
to DQs as “DQ.” The DQ term is to be interpreted as any
and all DQ collectively, unless specifically stated otherwise.
Additionally, each chip is divided into 2 bytes, the lower byte
and upper byte. For the lower byte (DQ0–DQ7), DM refers
to LDM and DQS refers to LDQS. For the upper byte (DQ8–
DQ15), DM refers to UDM and DQS refers to UDQS.
Complete functionality is described throughout the
document and any page or diagram may have been
simplified to convey a topic and may not be inclusive of all
requirements.
Any specific requirement takes precedence over a general
statement.
•
•
INITIALIZATION
DDR2 SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than those
specified may result in undefined operation. The following
sequence is required for power up and initialization and is
shown in Figure 4 on page 6.
1.
Applying power; if CKE is maintained below 0.2 x
V
CCQ
, outputs remain disabled. To guarantee R
TT
(ODT
resistance) is off, V
REF
must be valid and a low level
must be applied to the ODT ball (all other inputs may be
undefined, I/Os and outputs must be less than V
CCQ
during
voltage ramp time to avoid DDR2 SDRAM device latch-up).
At least one of the following two sets of conditions (A or B)
must be met to obtain a stable supply state (stable supply
defined as V
CC
, V
CCQ
, V
REF
, and V
TT
are between their
minimum and maximum values as stated in Table 5):
A.
(single power source) The V
CC
voltage ramp from
300mV to V
CC
(MIN) must take no longer than 200ms;
during the V
CC
voltage ramp, |V
CC -
V
CCQ
|
≤
0.3V.
Once supply voltage ramping is complete (when V
CCQ
crosses V
CC
(MIN)), Table20 specifications apply.
• V
CC
, V
CCQ
are driven from a single power converter
output
• V
TT
is limited to 0.95V MAX
• V
REF
tracks V
CCQ/2
; V
REF
must be within ±0.3V with
respect to V
CCQ/2
during supply ramp time
• V
CCQ
≥
V
REF
at all times
B.
(multiple power sources) V
CC
≥
V
CCQ
must be
maintained during supply voltage ramping, for both AC
and DC levels, until supply voltage ramping completes
(V
CCQ
crosses V
CC
[MIN]). Once supply voltage
ramping is complete, Table 5 specifications apply.
• Apply V
CC
before or at the same time as V
CCQ
; V
CC
voltage ramp time must be
≤
200ms from when V
CC
ramps from 300mV to V
CC
(MIN)
• Apply V
CCQ
before or at the same time as V
TT
; the
V
CCQ
voltage ramp time from when V
CC
(MIN) is
achieved to when V
CCQ
(MIN) is achieved must
be
≤
500ms; while V
CC
is ramping, current can be
supplied from V
CC
through the device to V
CCQ
5
Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
www.microsemi.com/pmgp
GENERAL NOTES
•
The functionality and the timing specifications discussed in
this data sheet are for the DLL-enabled mode of operation.
© 2011 Microsemi Corporation. All rights reserved.
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2011
Rev. 14
DIY/Open Source Hardware
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