EN29GL064
EN29GL064
64 Megabit (8192K x 8-bit / 4096K x 16-bit) Flash Memory
Page mode Flash Memory, CMOS 3.0 Volt-only
FEATURES
•
Single power supply operation
- Full voltage range: 2.7 to 3.6 volts read and
write operations
•
High performance
- Access times as fast as 70 ns
•
8-word/16-byte page read buffer
•
16-word/32-byte write buffer reduces overall
programming time for multiple-word updates
•
Secured Silicon Sector region
- 128-word/256-byte sector for permanent,
secure identification through an 8-word/16-
byte random Electronic Serial Number
- Can be programmed and locked at the factory
or by the customer
•
Flexible Sector Architecture:
- Uniform sector models:
One hundred and twenty-eight uniform
32Kword/64Kbyte sectors
- Boot sector models:
Eight 8-Kbyte boot sectors on Top or Bottom
and one hundred twenty-seven 32Kword /
64Kbyte sectors.
•
Suspend and Resume commands for
Program and Erase operations
•
Write operation status bits indicate program
and erase operation completion
•
Support for CFI (Common Flash Interface)
•
Persistent methods of Advanced Sector
Protection
•
WP#/ACC input
- Accelerates programming time (when V
HH
is
applied) for greater throughput during system
production
- Protects first or last sector regardless of
sector protection settings
•
Hardware reset input (RESET#) resets
device
•
Ready/Busy# output (RY/BY#) detects
program or erase cycle completion
•
Minimum 100K program/erase endurance
cycles.
•
Package Options
- 56-pin TSOP
- 64-ball 11mm x 13mm BGA
•
Industrial Temperature Range.
GENERAL DESCRIPTION
The EN29GL064 offers a fast page access time of 25 ns with a corresponding random access time as
fast as 70 ns. It features a Write Buffer that allows a maximum of 16 words/32 bytes to be programmed
in one operation, resulting in faster effective programming time than standard programming algorithms.
This makes the device ideal for today’s embedded applications that require higher density, better
performance and lower power consumption.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
1
Elite Semiconductor Memory Technology Inc.
Rev. O, Issue Date: 2016/07/29
EN29GL064
CONNECTION DIAGRAMS
Figure 1. 56-pin Standard TSOP (Top View)
RFU
RFU
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
A21
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
RFU
RFU
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
RFU
RFU
A16
BYTE#
Vss
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Vcc
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
Vss
CE#
A0
RFU
V
cc
Note:
RFU= Reserved for future use
Pin 43 and Pin 29 must connect to Vcc at the same time
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
2
Elite Semiconductor Memory Technology Inc.
Rev. O, Issue Date: 2016/07/29
EN29GL064
Figure 2. 64-ball Ball Grid Array (Top View, Balls Facing Down)
A8
RFU
A7
A13
A6
A9
A5
WE#
A4
RY / BY#
A3
A7
A2
A3
A1
RFU
B8
RFU
B7
A12
B6
A8
B5
RESET#
B4
WP# / ACC
B3
A17
B2
A4
B1
RFU
C8
RFU
C7
A14
C6
A10
C5
A21
C4
A18
C3
A6
C2
A2
C1
RFU
D8
VCC
D7
A15
D6
A11
D5
A19
D4
A20
D3
A5
D2
A1
D1
RFU
E8
VSS
E7
A16
E6
DQ7
E5
DQ5
E4
DQ2
E3
DQ0
E2
A0
E1
RFU
F8
RFU
F7
G8
RFU
G7
H8
RFU
H7
VSS
H6
DQ6
H5
DQ4
H4
DQ3
H3
DQ1
H2
VSS
H1
RFU
BYTE# DQ15 / A -1
F6
DQ14
F5
DQ12
F4
DQ10
F3
DQ8
F2
CE#
F1
VCC
G6
DQ13
G5
VCC
G4
DQ11
G3
DQ9
G2
OE#
G1
RFU
Note:
RFU= Reserved for future use
Pin D8 and Pin F1 must connect to Vcc at the same time
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
3
Elite Semiconductor Memory Technology Inc.
Rev. O, Issue Date: 2016/07/29
EN29GL064
TABLE 1. PIN DESCRIPTION
Pin Name
A21–A0
DQ0-DQ14
DQ15 / A-1
CE#
OE#
RESET#
RY/BY#
WE#
Vcc
Vss
BYTE#
WP#/ACC
RFU
A21–A0
Data input/output.
DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
Chip Enable
Output Enable
Hardware Reset Pin
Ready/Busy Output
Write Enable
Supply Voltage (2.7-3.6V)
Ground
Byte/Word mode selection
Write Protect / Acceleration Pin
(WP# has an internal pull-up; when
unconnected, WP# is at V
IH
.)
Reserved for future use.
Not Connected to anything
A0 – A21
FIGURE 3. LOGIC DIAGRAM
EN29GL064
Function
DQ0 – DQ15
(A-1)
CE#
OE#
WE#
Reset#
WP#/ACC
Byte#
RY/BY#
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
4
Elite Semiconductor Memory Technology Inc.
Rev. O, Issue Date: 2016/07/29
EN29GL064
Table 2. PRODUCT SELECTOR GUIDE
Product Number
Speed Option
Full Voltage Range: Vcc=2.7 – 3.6 V
EN29GL064
-70
70
25
70
25
Max Access Time, ns (t
acc
)
Max Page Read Access, ns(t
pacc
)
Max CE# Access, ns (t
ce
)
Max OE# Access, ns (t
oe
)
BLOCK DIAGRAM
Vcc
Vss
RY/BY#
Block Protect Switches
DQ0-DQ15 (A-1)
Erase Voltage Generator
State
Control
P rogram Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Input/Output Buffers
WE#
Command
Register
CE#
OE#
Data Latch
Y-Decoder
Address Latch
STB
Y-Gating
Vcc Detector
Timer
X-Decoder
Cell Matrix
A
0
-A
M ax
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5
Elite Semiconductor Memory Technology Inc.
Rev. O, Issue Date: 2016/07/29
Microcontroller MCU
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