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MCIMX6S5EVM10ACR

Description
processors - application specialized
Categorysemiconductor    Other integrated circuit (IC)   
File Size1MB,167 Pages
ManufacturerFREESCALE (NXP)
Environmental Compliance  
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MCIMX6S5EVM10ACR Overview

processors - application specialized

NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMX6SDLCEC
Rev. 7, 10/2016
i.MX 6Solo/6DualLite
Applications Processors
for Consumer Products
MCIMX6SxExxxxxB
MCIMX6SxExxxxxC
MCIMX6UxExxxxxB
MCIMX6UxExxxxxC
MCIMX6SxDxxxxxB
MCIMX6SxDxxxxxC
MCIMX6UxDxxxxxB
MCIMX6UxDxxxxxC
Package Information
Plastic Package
BGA Case 2240 21 x 21 mm, 0.8 mm pitch
Ordering Information
See
Table 1 on page 3
1
Introduction
1
The i.MX 6Solo/6DualLite processors represent the
latest achievement in integrated multimedia-focused
products offering high performance processing with
lower cost, as well as optimization for low power
consumption.
The processors feature advanced implementation of
single/dual ARM
®
Cortex
®
-A9 core, which operates at
speeds of up to 1 GHz. They include 2D and 3D graphics
processors, 1080p video processing, and integrated
power management. Each processor provides a 32/64-bit
DDR3/DDR3L/LPDDR2-800 memory interface and a
number of other interfaces for connecting peripherals,
such as WLAN, Bluetooth
®
, GPS, hard drive, displays,
and camera sensors.
The i.MX 6Solo/6DualLite processors are specifically
useful for applications such as:
• Web and multimedia tablets
2
3
4
5
6
7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.3 Updated Signal Naming Convention . . . . . . . . . . . .9
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.1 Special Signal Considerations . . . . . . . . . . . . . . . .21
3.2 Recommended Connections for Unused Analog
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .23
4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . .23
4.2 Power Supplies Requirements and Restrictions. . .33
4.3 Integrated LDO Voltage Regulator Parameters . . .34
4.4 PLL’s Electrical Characteristics. . . . . . . . . . . . . . . .37
4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . .38
4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . .39
4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . .44
4.8 Output Buffer Impedance Parameters . . . . . . . . . .48
4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . .51
4.10 General-Purpose Media Interface (GPMI) Timing .63
4.11 External Peripheral Interface Parameters. . . . . . . .71
Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . .133
5.1 Boot Mode Configuration Pins . . . . . . . . . . . . . . .133
5.2 Boot Device Interface Allocation. . . . . . . . . . . . . .134
Package Information and Contact Assignments . . . . . .135
6.1 Updated Signal Naming Convention . . . . . . . . . .135
6.2 21x21 mm Package Information . . . . . . . . . . . . . .136
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
© 2012-2016 NXP B.V.
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