DRAM MODULE
KMM5322104CKU/CKUG
KMM5322104CKU/CKUG Fast Page Mode with Extended Data Out
2M x 32 DRAM SIMM using 2Mx8 , 2K Refresh, 5V
GENERAL DESCRIPTION
The Samsung KMM5322104CKU is a 2Mx32bits
RAM
high
density
memory
module.
The
Dynamic
Samsung
FEATURES
• Part Identification
- KMM5322104CKU(2048 cycles/32ms Ref, SOJ, Solder)
- KMM5322104CKUG(2048 cycles/32ms Ref, SOJ, Gold)
• Fast Page Mode with Extended Data Out
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• TTL compatible inputs and outputs
• Single +5V±10% power supply
• JEDEC standard PDPin & pinout
• PCB : Height(1000mil), single sided component
KMM5322104CKU consists of four CMOS 2Mx8bits DRAMs in
28-pin SOJ package mounted on a 72-pin glass-epoxy sub-
strate. A 0.1 or 0.22uF decoupling capacitor is mounted on the
printed circuit board for each DRAM. The KMM5322104CKU is
a Single In-line Memory Module with edge connections and is
intended for mounting into 72 pin edge connector sockets.
PERFORMANCE RANGE
Speed
-5
-6
t
RAC
50ns
60ns
t
CAC
13ns
15ns
t
RC
90ns
110ns
t
HPC
25ns
30ns
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Symbol
V
SS
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
Res(A11)
Vcc
A8
A9
Res(RAS1)
RAS0
NC
NC
Pin
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Symbol
NC
NC
Vss
CAS0
CAS2
CAS3
CAS1
RAS0
Res(RAS1)
NC
W
NC
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
Vcc
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
PD1
PD2
PD3
PD4
NC
Vss
PIN NAMES
Pin Name
A0 - A10
DQ0 - DQ31
W
RAS0
CAS0 - CAS3
PD1 -PD4
Vcc
Vss
NC
Res
Function
Address Inputs
Data In/Out
Read/Write Enable
Row Address Strobe
Column Address Strobe
Presence Detect
Power(+5V)
Ground
No Connection
Reserved Pin
PRESENCE DETECT PINS (Optional)
Pin
PD1
PD2
PD3
PD4
50NS
NC
NC
Vss
Vss
60NS
NC
NC
NC
NC
* Pin connection changing available
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
DRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
KMM5322104CKU/CKUG
RAS0
CAS0
DQ0
DQ1
DQ2
CAS
DQ3
U0
DQ4
DQ5
OE
DQ6
W A0-A10 DQ7
RAS
DQ0-DQ7
CAS1
DQ0
DQ1
DQ2
CAS
DQ3
U1
DQ4
DQ5
OE
DQ6
W A0-A10 DQ7
RAS
DQ8-DQ15
CAS2
DQ0
DQ1
DQ2
CAS
DQ3
U2
DQ4
DQ5
OE
DQ6
W A0-A10 DQ7
RAS
DQ16-DQ23
CAS3
DQ0
DQ1
DQ2
CAS
DQ3
U3
DQ4
DQ5
OE
DQ6
W A0-A10 DQ7
RAS
DQ24-DQ31
W
A0-A10
Vcc
.1 or .22uF Capacitor
for each DRAM
Vss
To all DRAMs
DRAM MODULE
ABSOLUTE MAXIMUM RATINGS *
Item
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
V
IN
, V
OUT
V
CC
T
stg
P
d
I
OS
KMM5322104CKU/CKUG
Rating
-1 to +7.0
-1 to +7.0
-55 to +150
4
50
Unit
V
V
°C
W
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to V
SS
, T
A
= 0 to 70°C)
Item
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
*1 : V
CC
+2.0V/20ns, Pulse width is measured at V
CC
.
*2 : -2.0V/20ns, Pulse width is measured at V
SS
.
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.4
-1.0
*2
Typ
5.0
0
-
-
Max
5.5
0
V
CC
+1
*1
0.8
Unit
V
V
V
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Symbol
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
I(L)
I
O(L)
V
OH
V
OL
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
I(L)
I
O(L)
V
OH
V
OL
Speed
-5
-6
Don′t care
-5
-6
-5
-6
Don′t care
-5
-6
Don′t care
Don′t care
KMM5322104CKU/CKUG
Min
-
-
Max
440
400
8
440
400
360
320
4
440
400
20
5
-
0.4
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
uA
V
V
-
-
-
-
-
-
-
-
-20
-5
2.4
-
: Operating Current * (RAS, CAS, Address cycling @
t
RC
=min)
: Standby Current (RAS=CAS=W=V
IH
)
: RAS Only Refresh Current * (CAS=V
IH
, RAS cycling @
t
RC
=min)
: EDO Mode Current * (RAS=V
IL
, CAS cycling :
t
HPC
=min)
: Standby Current (RAS=CAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @
t
RC
=min)
: Input Leakage Current (Any input 0≤V
IN
≤Vcc+0.5V,
all other pins not under test=0 V)
: Output Leakage Current(Data Out is disabled, 0V≤V
OUT
≤Vcc)
: Output High Voltage Level (I
OH
= -5mA)
: Output Low Voltage Level (I
OL
= 4.2mA)
* NOTE
: I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
and I
CC3
, address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one EDO mode cycle,
t
HPC
.
DRAM MODULE
CAPACITANCE
(T
A
= 25°C, V
CC
=5V, f = 1MHz)
Item
Input capacitance[A0-A10]
Input capacitance[W]
Input capacitance[RAS0]
Input capacitance[CAS0 - CAS3]
Input/Output capacitance[DQ0-31]
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
DQ
Min
-
-
-
-
-
KMM5322104CKU/CKUG
Max
35
40
40
20
20
Unit
pF
pF
pF
pF
pF
AC CHARACTERISTICS
(0°C≤T
A
≤70°C,
V
CC
=5.0V±10%. See notes 1,2.)
Test condition : V
ih
/V
il
=2.4/0.8V, V
oh
/V
ol
=2.0/0.8V, output loading CL=100pF
Parameter
Random read or write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay from CAS
Transition time(rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in set-up time
Data-in hold time
Refresh period
Write command set-up time
CAS setup time(CAS-before-RAS refresh)
CAS hold time(CAS-before-RAS refresh)
RAS precharge to CAS hold time
CAS precharge time (C-B-R counter test)
Symbol
-5
Min
90
50
13
25
3
3
2
30
50
13
40
8
20
15
5
0
10
0
8
25
0
0
0
10
10
13
8
0
8
32
0
5
10
5
20
0
5
10
5
20
10K
37
25
10K
13
50
3
3
2
40
60
15
50
10
20
15
5
0
10
0
10
30
0
0
0
10
10
15
10
0
10
32
10K
45
30
10K
15
50
Max
Min
110
60
15
30
-6
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
7
9
9
8
8
13
4
10
3,4,10
3,4,5
3,10
3
6,11,12
2
Note
t
RC
t
RAC
t
CAC
t
AA
t
CLZ
t
CEZ
t
T
t
RP
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
t
RCS
t
RCH
t
RRH
t
WCH
t
WP
t
RWL
t
CWL
t
DS
t
DH
t
REF
t
WCS
t
CSR
t
CHR
t
RPC
t
CPT
DRAM MODULE
Test condition : V
ih
/V
il
=2.4/0.8V, V
oh
/V
ol
=2.0/0.8V, output loading CL=100pF
Parameter
Access time from CAS precharge
Hyper page mode cycle time
CAS precharge time from (Hyper Page Cycle)
RAS pulse width (Hyper Page Cycle)
RAS hold time from CAS precharge
W to RAS precharge time (C-B-R refresh)
W to RAS hold time (C-B-R refresh)
Output data hold time
Output buffer turn off delay from RAS
Output buffer turn off delay from W
W to data delay
W pulse width (Hyper Page Cycle)
Symbol
-5
Min
25
8
50
30
10
10
5
3
3
15
5
13
13
200K
Max
30
KMM5322104CKU/CKUG
AC CHARACTERISTICS
(0°C≤T
A
≤70°C,
V
CC
=5.0V±10%. See notes 1,2.)
-6
Min
30
10
60
35
10
10
5
3
3
15
5
15
15
200K
Max
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6,11,12
6,11
Note
3
13
t
CPA
t
HPC
t
CP
t
RASP
t
RHCP
t
WRP
t
WRH
t
DOH
t
REZ
t
WEZ
t
WED
t
WPE
NOTES
1. An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
2. V
IH
(min) and V
IL
(max) are reference levels for measuring
timing of input signals. Transition times are measured
between V
IH
(min) and V
IL
(max) and are assumed to be 5ns
for all inputs.
3. Measured with a load equivalent to 2 TTL loads and 100pF.
4. Operation within the
t
RCD
(max) limit insures that
t
RAC
(max)
can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then
access time is controlled exclusively by
t
CAC
.
5. Assumes that
t
RCD
≥
t
RCD
(max).
6. This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V
OH
or
V
OL
.
7.
t
WCS
is non-restrictive operating parameter. It is included in
the data sheet as electrical characteristics only. If
t
WCS
≥
t
WCS
(min), the cycle is an early write cycle and the data
out pin will remain high impedance for the duration of the
cycle.
8. Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
9. These parameters are referenced to the CAS leading edge in
early write cycles and to the W leading edge in read-write
cycles.
10. Operation within the
t
RAD
(max) limit insures that
t
RAC
(max)
can be met.
t
RAD
(max) is specified as reference point only. If
t
RAD
is greater than the specified
t
RAD
(max) limit, then
access time is controlled by
t
AA
.
11.
t
CEZ
(max),
t
REZ
(max),
t
WEZ
(max) and
t
OEZ
(max) define the
time at which the output achieves the open circuit condition
and are not referenced to output voltage level.
12. If RAS goes to high before CAS high going, the open circuit
condtion of the output is achieved by CAS high going. If CAS
goes to high before RAS high going, the open circuit condtion
of the output is achieved by RAS high going.
13.
t
ASC
≥
t
CP min
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