12-Bit Differential Input 200kSPS SAR ADC
ISL267817
The ISL267817 is a 12-bit, 200kSPS sampling SAR-type ADC
which features excellent linearity over supply and temperature
variations, and provides a drop-in compatible alternative to all
ADS7817 performance grades. The robust, fully-differential
input offers high impedance to minimize errors due to leakage
currents, and the specified measurement accuracy is
maintained with input signals up to the supply rails.
The reference accepts inputs between 0.1V to 2.5V, providing
design flexibility in a wide variety of applications. The
ISL267817 also features up to 8kV Human Body Model ESD
survivability.
The serial digital interface is SPI compatible and is easily
interfaced to popular FPGAs and microcontrollers. Operating
from a 5V supply, power dissipation is 2.15mW at a sampling
rate of 200kSPS, and just 25µW between conversions utilizing
the Auto Power-Down mode, making the ISL267817 an
excellent solution for remote industrial sensors and
battery-powered instruments. It is available in the compact,
industry-standard 8 Lead SOIC and MSOP packages and is
specified for operation over the industrial temperature range
(-40°C to +85°C).
Features
• Drop-In Compatible with ADS7817 (All Performance Grades)
• Differential Input
• Simple SPI-compatible Serial Digital Interface
• Guaranteed No Missing Codes
• 200kHz Sampling Rate
• +4.75V to +5.25V Supply
• Low 2.15mW Operating Power (200kSPS)
• Power-down Current between Conversions: 3µA
• Excellent Differential Non-Linearity (1.0LSB max)
• Low THD: -85dB (typ)
• Pb-Free (RoHS Compliant)
• Available in SOIC and MSOP Packages
Applications
• Remote Data Acquisition
• Battery Operated Systems
• Industrial Process Control
• Energy Measurement
• Data Acquisition Systems
• Pressure Sensors
• Flow Controllers
1.00
VREF
DAC
+VCC
0.75
0.50
0.25
+IN
–IN
DAC
SAR
LOGIC
SERIAL
INTERFACE
DCLOCK
DOUT
CS/SHDN
0.00
-0.25
-0.50
VREF
-0.75
GND
-1.00
0
512
1024 1536 2048 2560 3072 3584 4096
FIGURE 1. BLOCK DIAGRAM
FIGURE 2. DIFFERENTIAL LINEARITY ERROR vs CODE
April 19, 2012
FN7877.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas Inc. 2011, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL267817
Typical Connection Diagram
VREF
+
0.1µF +
10µF
+5V SUPPLY
VREF
+VCC
REF
P-P
REF
P-P
+IN
–IN
DCLOCK
DOUT
µP/µC
GND
CS/SHDN
SERIAL
INTERFACE
Pin Configuration
ISL267817
(8 LD SOIC, MSOP)
TOP VIEW
VREF 1
+IN 2
–IN
3
GND 4
8 +VCC
7 DCLOCK
6 DOUT
5 CS/SHDN
Pin Descriptions
PIN NAME
VREF
+IN
–IN
GND
CS/SHDN
DOUT
DCLOCK
+VCC
PIN NUMBER
1
2
3
4
5
6
7
8
DESCRIPTION
Reference Input
Non Inverting Input
Inverting Input
Ground
Low = Chip Select, High = Shutdown
Serial Output Data
Data Clock
Power Supply
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL267817IBZ
ISL267817IUZ
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for the
ISL267817.
For more information on MSL please see tech brief
TB363.
PART
MARKING
267817 IBZ
67817
+VCC RANGE
(V)
4.75 to 5.25
4.75 to 5.25
TEMP RANGE
(°C)
-40°C to +85°C
-40°C to +85°C
PACKAGE
8 Ld SOIC
8 Ld MSOP
PKG.
DWG. #
M8.15
M8.118
2
FN7877.2
April 19, 2012
ISL267817
Table of Contents
Typical Connection Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ADC Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Down/Standby Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Static Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power vs Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
12
13
13
13
13
13
13
Serial Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package Outline Drawing (M8.15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Package Outline Drawing (M8.118). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3
FN7877.2
April 19, 2012
ISL267817
Absolute Maximum Ratings
Any Pin to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
Analog Input to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +VCC+0.3V
Digital I/O to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +VCC+0.3V
Digital Input Voltage to GND . . . . . . . . . . . . . . . . . . . . . .-0.3V to +VCC+0.3V
Maximum Current In to Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 8kV
Machine Model (Tested per JESD22-A115B) . . . . . . . . . . . . . . . . . 400V
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . 1.5kV
Latch Up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical)
θ
JA
(°C/W)
θ
JC
(°C/W)
8 Ld SOIC Package (Notes 4, 5). . . . . . . . . .
120
64
8 Ld MSOP Package (Notes 4, 5). . . . . . . . .
165
64
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379
for details.
5. For
θ
JC
, the “case temp” location is taken at the package top center.
Electrical Specifications
SYMBOL
+VCC = +5V, f
DCLOCK
= 3.2MHz, f
S
= 200kSPS, V
REF
= 2.5V; V
CM
= V
REF
, Typical values are at T
A
= +25°C.
Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
ANALOG INPUT (Note 7)
|AIN|
Full-Scale Input Span
Absolute Input Voltage
+IN – (–IN)
+IN
–IN
C
VIN
I
LEAK
Input Capacitance
Input DC Leakage Current
Sample/Hold Mode
-1
-VREF
-0.3
-0.3
13/6
0.01
1
+VREF
+VCC +0.3
+VCC +0.3
V
V
V
pF
µA
SYSTEM PERFORMANCE
N
Resolution
No Missing Codes
INL
DNL
OFFSET
GAIN
CMRR
PSRR
Integral Nonlinearity
Differential Nonlinearity
Zero-Code Error
Gain Error
Common-Mode Rejection
Power Supply Rejection
12
12
-1
-1
-6
-4
±0.5
±0.4
±0.25
±0.12
80
82
1
1
6
4
Bits
Bits
LSB
LSB
LSB
LSB
dB
dB
SAMPLING DYNAMICS
t
CONV
t
ACQ
f
max
Conversion Time
Acquisition Time
Throughput Rate
f
DCLOCK
= 3.2MHz
1.5
200
12
Clk Cycles
Clk Cycles
kSPS
DYNAMIC CHARACTERISTICS
THD
Total Harmonic Distortion
V
IN
= 5.0V
P-P
at f
IN
= 1kHz
V
IN
= 5.0V
P-P
at f
IN
= 5kHz
SINAD
SFDR
BW
Signal-to (Noise + Distortion) Ratio
Spurious Free Dynamic Range
Full Power Bandwidth
V
IN
= 5.0V
P-P
at f
IN
= 1kHz
V
IN
= 5.0V
P-P
at f
IN
= 1kHz
At –3dB
-85
-84
71
85
15
dB
dB
dB
dB
MHz
4
FN7877.2
April 19, 2012
ISL267817
Electrical Specifications
SYMBOL
+VCC = +5V, f
DCLOCK
= 3.2MHz, f
S
= 200kSPS, V
REF
= 2.5V; V
CM
= V
REF
, Typical values are at T
A
= +25°C.
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
REFERENCE INPUT
VREF
VREFLEAK
VREF Input Range
Current Drain
f
SAMPLE
= 12.5kHz
CS/SHDN = +VCC
0.1
-100
-20
-3
4
0.23
0.01
2.5
100
20
3
V
µA
µA
µA
DIGITAL INPUT/OUTPUT
Logic Family
V
IH
V
IL
V
OH
V
OL
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output Coding
I
LEAK
C
IN
I
OZ
C
OUT
Input Leakage Current
Input Capacitance
Floating-State Output Current
Floating-State Output Capacitance
-1
5
-1
10
1
I
OH
= –250µA
I
OL
= 250µA
3
-0.3
3.5
0.4
Two’s Complement
1
µA
pF
µA
pF
CMOS
+VCC + 0.3
0.8
V
V
V
V
POWER REQUIREMENTS
V
CC
I
CC
Supply Voltage Range
Supply Current
f
SAMPLE
= 12.5kHz (Notes 8, 9)
f
SAMPLE
= 12.5kHz (Note 9)
Power Down Current
CS/SHDN = +VCC, f
SAMPLE
= 0Hz
4.75
430
38
223
0.5
3
5.25
800
V
µA
µA
µA
µA
TEMPERATURE RANGE
Specified Performance
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. The absolute voltage applied to each analog input must be between GND and +VCC to guarantee datasheet performance.
8. f
DCLOCK
= 3.2MHz, CS/SHDN = +VCC for 241 clock cycles out of every 256.
9. See “Power vs Throughput Rate” on page 13 for more information regarding lower sample rates.
-40
+85
°C
Timing Specifications
SYMBOL
t
SMPL
t
CONV
f
CYC
t
CSD
t
SUCS
t
hDO
Limits established by characterization and are not production tested. +VCC = 5V, f
DCLOCK
= 3.2MHz, f
S
= 200kSPS,
V
REF
= 2.5V; V
CM
= V
REF
. Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
Analog Input Sample Time
Conversion Time
Throughput Rate
CS/SHDN Falling Edge to DCLOCK Low
CS/SHDN Falling Edge to DCLOCK Rising Edge
DCLOCK Falling Edge to Current DOUT Not Valid
30
15
TEST CONDITIONS
MIN
(Note 6)
1.5
12
200
0
TYP
MAX
(Note 6)
2.0
UNITS
Clk Cycles
Clk Cycles
kHz
ns
ns
ns
5
FN7877.2
April 19, 2012
GD32 MCU
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