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ICS9250YG-24LF

Description
PLL Based Clock Driver, 22 True Output(s), 0 Inverted Output(s), PDSO56, 0.240 INCH, TSSOP-56
Categorylogic    logic   
File Size83KB,9 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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ICS9250YG-24LF Overview

PLL Based Clock Driver, 22 True Output(s), 0 Inverted Output(s), PDSO56, 0.240 INCH, TSSOP-56

ICS9250YG-24LF Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP,
Contacts56
Reach Compliance Codecompliant
Input adjustmentSTANDARD
JESD-30 codeR-PDSO-G56
JESD-609 codee3
length14 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Number of functions1
Number of inverted outputs
Number of terminals56
Actual output times22
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.5 ns
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width6.1 mm
Base Number Matches1
Integrated
Circuit
Systems, Inc.
ICS9250-24
Integrated Buffers for PIII™
Recommended Application:
General purpose peripheral clk gen, also for IA64.
Output Features:
12 - PCI clocks @ 3V
2 - 48MHz clocks
6 - 3V66 66MHz reference output
2 - 14.318 reference output
Features:
Effective power management scheme through PD#
14.318MHz reference input
66MHz reference input
Key Specifications:
48MHz Output Jitter: <350ps
3V66 to PCI Skew: 1.5 to 3.5ns
PCI to PCI Skew: <500ps
3V66 to 3V66 Skew: <250ps
GND
14.318_IN
VDD
66_IN
GND
PCICLK0
PCICLK1
VDD
GND
PCICLK2
PCICLK3
VDD
GND
PCICLK4
PCICLK5
VDD
PCICLK6
PCICLK7
GND
VDD
PCICLK8
PCICLK9
GND
PCICLK10
PCICLK11
VDD
FS0
FS1
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDD
REF-1
REF-0
GND
VDD
3V66-5
3V66-4
GND
GND
3V66-3
3V66-2
VDD
VDD
3V66-1
3V66-0
GND
VDD
GND
AVDD
48MHz-1
48MHz-0
AGND
FS2
PD#
VDD
GND
SCLK
SDATA
56-Pin 300mil SSOP & TSSOP
Block Diagram
14.318_IN
PLL
2
Functionality
FS0
REF (1:0)
FS1
0
0
1
1
0
0
1
1
FS2
0
1
0
1
0
1
0
1
Description
All outputs on
PCI (7:0) off
PCI (5:0) off
All PCI off
Tristate
3V66-5 off
REF (1:0) off
48MHz-1 off
ICS9250-24
Details
All outputs on
Pins 18, 17, 15, 14, 11,
10, 7, 6 held LOW
Pins 15, 14, 11, 10, 7, 6
held LOW
All PCI outputs held LOW
All outputs high
impedance
Pin 51 held LOW
Pins 55, 54 held LOW
Pin 37 held LOW
0
0
2
48MHz (1:0)
0
Control
SDATA
SCLK
FS (2:0)
PD#
Logic
Config.
Reg.
0
1
1
1
3V66 (5:0)
PCICLK (11:0)
66_IN
/2
Delay
6
12
1
Power Groups
AGND = Analog ground
AVDD = Analog power
0390C—11/06/02

ICS9250YG-24LF Related Products

ICS9250YG-24LF ICS9250YG-24 ICS9248YF-24 ICS9248YF-24LF
Description PLL Based Clock Driver, 22 True Output(s), 0 Inverted Output(s), PDSO56, 0.240 INCH, TSSOP-56 PLL Based Clock Driver, 22 True Output(s), 0 Inverted Output(s), PDSO56, 0.240 INCH, TSSOP-56 PLL Based Clock Driver, 22 True Output(s), 0 Inverted Output(s), PDSO56, 0.300 INCH, SSOP-56 PLL Based Clock Driver, 22 True Output(s), 0 Inverted Output(s), PDSO56, 0.300 INCH, SSOP-56
Is it lead-free? Lead free Contains lead Contains lead Lead free
Is it Rohs certified? conform to incompatible incompatible conform to
Parts packaging code TSSOP TSSOP SSOP SSOP
package instruction TSSOP, TSSOP, SSOP, SSOP,
Contacts 56 56 56 56
Reach Compliance Code compliant compliant compliant compliant
Input adjustment STANDARD STANDARD STANDARD STANDARD
JESD-30 code R-PDSO-G56 R-PDSO-G56 R-PDSO-G56 R-PDSO-G56
JESD-609 code e3 e0 e0 e3
length 14 mm 14 mm 18.415 mm 18.415 mm
Logic integrated circuit type PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER
Number of functions 1 1 1 1
Number of terminals 56 56 56 56
Actual output times 22 22 22 22
Maximum operating temperature 70 °C 70 °C 70 °C 70 °C
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP SSOP SSOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260 240 225 260
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
Same Edge Skew-Max(tskwd) 0.5 ns 0.5 ns 0.5 ns 0.5 ns
Maximum seat height 1.2 mm 1.2 mm 2.794 mm 2.794 mm
Maximum supply voltage (Vsup) 3.465 V 3.465 V 3.465 V 3.465 V
Minimum supply voltage (Vsup) 3.135 V 3.135 V 3.135 V 3.135 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V
surface mount YES YES YES YES
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal surface Matte Tin (Sn) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Matte Tin (Sn)
Terminal form GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.5 mm 0.5 mm 0.635 mm 0.635 mm
Terminal location DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature 30 20 30 30
width 6.1 mm 6.1 mm 7.5 mm 7.5 mm
Base Number Matches 1 1 1 1

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