INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4040
12-stage binary ripple counter
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
12-stage binary ripple counter
FEATURES
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4040 are high-speed Si-gate CMOS
devices and are pin compatible with “4040” of the “4000B”
series. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4040 are 12-stage binary ripple counters
with a clock input (CP), an overriding asynchronous
master reset input (MR) and twelve parallel outputs
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT4040
(Q
0
to Q
11
). The counter advances on the HIGH-to-LOW
transition of CP.
A HIGH on MR clears all counter stages and forces all
outputs LOW, independent of the state of CP.
Each counter stage is a static toggle flip-flop.
APPLICATIONS
•
Frequency dividing circuits
•
Time delay circuits
•
Control counters
TYPICAL
SYMBOL
t
PHL
/ t
PLH
PARAMETER
propagation delay
CP to Q
0
Q
n
to Q
n+1
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
maximum clock frequency
input capacitance
power dissipation capacitance per package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
14
8
90
3.5
20
16
8
79
3.5
20
ns
ns
MHz
pF
pF
HCT
UNIT
December 1990
2
Philips Semiconductors
Product specification
12-stage binary ripple counter
PIN DESCRIPTION
PIN NO.
8
9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1
10
11
16
SYMBOL
GND
Q
0
to Q
11
CP
MR
V
CC
NAME AND FUNCTION
ground (0 V)
parallel outputs
74HC/HCT4040
clock input (HIGH-to-LOW, edge-triggered)
master reset input (active HIGH)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
12-stage binary ripple counter
74HC/HCT4040
FUNCTION TABLE
INPUTS
CP
↑
↓
X
Notes
MR
L
L
H
OUTPUTS
Q
n
no change
count
L
Fig.4 Functional diagram.
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑
= LOW-to-HIGH clock
transition
↓
= HIGH-to-LOW clock
transition
Fig.5 Logic diagram.
Fig.6 Timing diagram.
December 1990
4
Philips Semiconductors
Product specification
12-stage binary ripple counter
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL PARAMETER
min.
t
PHL
/ t
PLH
propagation delay
CP to Q
0
propagation delay
Q
n
to Q
n+1
propagation delay
MR to Q
n
output transition time
+25
typ.
47
17
14
28
10
8
61
22
18
19
7
6
80
16
14
80
16
14
50
10
9
6.0
30
35
14
5
4
22
8
6
8
3
2
27
82
98
−40
to
+85
max. min.
150
30
26
100
20
17
185
37
31
75
15
13
100
20
17
100
20
17
65
13
11
4.8
24
28
max.
190
38
33
125
25
21
230
46
39
95
19
16
120
24
20
120
24
20
75
15
13
4.0
20
24
−40
to
+125
min.
max.
225
45
38
150
30
26
280
56
48
110
22
19
ns
74HC/HCT4040
TEST CONDITIONS
UNIT
V
CC
WAVEFORMS
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.7
t
PHL
/ t
PLH
ns
Fig.7
t
PHL
ns
Fig.7
t
THL
/ t
TLH
ns
Fig.7
t
W
clock pulse width
HIGH or LOW
master reset pulse
width; HIGH
removal time
MR to CP
maximum clock pulse
frequency
ns
Fig.7
t
W
ns
Fig.7
t
rem
ns
Fig.7
f
max
MHz
Fig.7
December 1990
5
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