XC5VLX330T-2FF1738I datasheet, PDF

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XC5VLX330T-2FF1738I: DescriptionField Programmable Gate Array, 25920 CLBs, 1265MHz, 331776-Cell, CMOS, PBGA1738, 42.50 X 42.50 MM, FBGA-1738; CategoryProgrammable logic devices Programmable logic; File Size314KB，13 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

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XC5VLX330T-2FF1738I Overview

Field Programmable Gate Array, 25920 CLBs, 1265MHz, 331776-Cell, CMOS, PBGA1738, 42.50 X 42.50 MM, FBGA-1738

XC5VLX330T-2FF1738I Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	XILINX
Parts packaging code	BGA
package instruction	BGA, BGA1738,42X42,40
Contacts	1738
Reach Compliance Code	not_compliant
ECCN code	3A001.A.7.A
Combined latency of CLB-Max	0.77 ns
JESD-30 code	S-PBGA-B1738
JESD-609 code	e0
length	42.5 mm
Humidity sensitivity level	4
Configurable number of logic blocks	25920
Number of entries	960
Number of logical units	331776
Output times	960
Number of terminals	1738
Maximum operating temperature	100 °C
Minimum operating temperature	-40 °C
organize	25920 CLBS
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA1738,42X42,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	225
power supply	1,2.5 V
Programmable logic type	FPGA
Certification status	Not Qualified
Maximum seat height	3.25 mm
Maximum supply voltage	1.05 V
Minimum supply voltage	0.95 V
Nominal supply voltage	1 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn63Pb37)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	42.5 mm
Base Number Matches	1

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Virtex-5 Family Overview

DS100 (v5.0) February 6, 2009

Product Specification

General Description

The Virtex®-5 family provides the newest most powerful features in the FPGA market. Using the second generation ASMBL™ (Advanced

Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choice

offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic

designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks,

including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIO™ technology with built-in digitally-

controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles

with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options.

Additional platform dependant features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity,

PCI Express® compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance

PowerPC® 440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of

performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5

FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength

of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP

designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and

connectivity capabilities. The Virtex-5 LXT, SXT, TXT, and FXT platforms include advanced high-speed serial connectivity and

link/transaction layer capability.

Summary of Virtex-5 FPGA Features

•

Five platforms LX, LXT, SXT, TXT, and FXT

−

Virtex-5 LX: High-performance general logic applications

−

Virtex-5 LXT: High-performance logic with advanced serial

−

•

connectivity

Virtex-5 SXT: High-performance signal processing

applications with advanced serial connectivity

Virtex-5 TXT: High-performance systems with double

density advanced serial connectivity

Virtex-5 FXT: High-performance embedded systems with

advanced serial connectivity

•

Advanced DSP48E slices

−

25 x 18, two’s complement, multiplication

−

Optional adder, subtracter, and accumulator

−

Optional pipelining

−

Optional bitwise logical functionality

−

Dedicated cascade connections

Flexible configuration options

−

SPI and Parallel FLASH interface

−

Multi-bitstream support with dedicated fallback

−

Auto bus width detection capability

System Monitoring capability on all devices

−

On-chip/Off-chip thermal monitoring

−

On-chip/Off-chip power supply monitoring

−

JTAG access to all monitored quantities

Integrated Endpoint blocks for PCI Express Designs

−

LXT, SXT, TXT, and FXT Platforms

−

Compliant with the PCI Express Base Specification 1.1

−

x1, x4, or x8 lane support per block

−

Works in conjunction with RocketIO™ transceivers

Tri-mode 10/100/1000 Mb/s Ethernet MACs

−

LXT, SXT, TXT, and FXT Platforms

−

RocketIO transceivers can be used as PHY or connect to

external PHY using many soft MII (Media Independent

Interface) options

reconfiguration logic

Cross-platform compatibility

−

LXT, SXT, and FXT devices are footprint compatible in the

same package using adjustable voltage regulators

•

Most advanced, high-performance, optimal-utilization,

FPGA fabric

−

Real 6-input look-up table (LUT) technology

−

Dual 5-LUT option

−

Improved reduced-hop routing

−

64-bit distributed RAM option

−

SRL32/Dual SRL16 option

Powerful clock management tile (CMT) clocking

−

Digital Clock Manager (DCM) blocks for zero delay

−

buffering, frequency synthesis, and clock phase shifting

PLL blocks for input jitter filtering, zero delay buffering,

frequency synthesis, and phase-matched clock division

•

36-Kbit block RAM/FIFOs

−

True dual-port RAM blocks

−

Enhanced optional programmable FIFO logic

−

Programmable

−

True dual-port widths up to x36

Simple dual-port widths up to x72

Built-in optional error-correction circuitry

Optionally program each block as two independent 18-Kbit

blocks

•

High-performance parallel SelectIO technology

−

1.2 to 3.3V I/O Operation

−

Source-synchronous interfacing using ChipSync™

−

technology

Digitally-controlled impedance (DCI) active termination

Flexible fine-grained I/O banking

High-speed memory interface support

•

RocketIO GTP transceivers 100 Mb/s to 3.75 Gb/s

−

LXT and SXT Platforms

RocketIO GTX transceivers 150 Mb/s to 6.5 Gb/s

−

TXT and FXT Platforms

PowerPC 440 Microprocessors

−

FXT Platform only

−

RISC architecture

−

7-stage pipeline

−

32-Kbyte instruction and data caches included

−

Optimized processor interface structure (crossbar)

65-nm copper CMOS process technology

1.0V core voltage

High signal-integrity flip-chip packaging available in standard

or Pb-free package options

countries. PowerPC is a trademark of IBM Corp. and is used under license. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property

of their respective owners.

DS100 (v5.0) February 6, 2009

www.xilinx.com

Product Specification

XC5VLX330T-2FF1738I Related Products

	XC5VLX330T-2FF1738I	XC5VLX330T-2FFG1738I	2104LHME140GSN3110	XC5VFX200T-2FF1738I	XC5VLX330-2FFG1760I	XC5VLX330-2FF1760I	XC5VSX240T-2FF1738I	XC5VSX240T-2FFG1738I
Description	Field Programmable Gate Array, 25920 CLBs, 1265MHz, 331776-Cell, CMOS, PBGA1738, 42.50 X 42.50 MM, FBGA-1738	Field Programmable Gate Array, 25920 CLBs, 1265MHz, 331776-Cell, CMOS, PBGA1738, 42.50 X 42.50 MM, LEAD FREE, FBGA-1738	CAP,AL2O3,100MF,80VDC,20% -TOL,20% +TOL	Field Programmable Gate Array, 16320 CLBs, 1265MHz, 196608-Cell, CMOS, PBGA1738, 42.50 X 42.50 MM, FBGA-1738	Field Programmable Gate Array, 25920 CLBs, 1265MHz, 331776-Cell, CMOS, PBGA1760, 42.50 X 42.50 MM, LEAD FREE, FBGA-1760	Field Programmable Gate Array, 25920 CLBs, 1265MHz, 331776-Cell, CMOS, PBGA1760, 42.50 X 42.50 MM, FBGA-1760	Field Programmable Gate Array, 18720 CLBs, 1265MHz, 239616-Cell, CMOS, PBGA1738, 42.50 X 42.50 MM, FBGA-1738	Field Programmable Gate Array, 18720 CLBs, 1265MHz, 239616-Cell, CMOS, PBGA1738, 42.50 X 42.50 MM, LEAD FREE, FBGA-1738
package instruction	BGA, BGA1738,42X42,40	BGA, BGA1738,42X42,40	,	BGA-1738	BGA-1760	BGA-1760	BGA-1738	BGA-1738
Reach Compliance Code	not_compliant	not_compliant	unknown	not_compliant	not_compliant	not_compliant	_compli	_compli
length	42.5 mm	42.5 mm	140 mm	42.5 mm	42.5 mm	42.5 mm	42.5 mm	42.5 mm
Number of terminals	1738	1738	2	1738	1760	1760	1738	1738
Maximum operating temperature	100 °C	100 °C	105 °C	100 °C	100 °C	100 °C	100 °C	100 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Package form	GRID ARRAY	GRID ARRAY	Screw Ends	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Is it Rohs certified?	incompatible	conform to	-	incompatible	conform to	incompatible	incompatible	conform to
Maker	XILINX	XILINX	-	XILINX	XILINX	XILINX	XILINX	XILINX
Parts packaging code	BGA	BGA	-	BGA	BGA	BGA	BGA	BGA
Contacts	1738	1738	-	1738	1760	1760	1738	1738
ECCN code	3A001.A.7.A	3A001.A.7.A	EAR99	3A001.A.7.A	3A001.A.7.A	3A001.A.7.A	-	-
Combined latency of CLB-Max	0.77 ns	0.77 ns	-	0.77 ns	0.77 ns	0.77 ns	0.77 ns	0.77 ns
JESD-30 code	S-PBGA-B1738	S-PBGA-B1738	-	S-PBGA-B1738	S-PBGA-B1760	S-PBGA-B1760	S-PBGA-B1738	S-PBGA-B1738
JESD-609 code	e0	e1	-	e0	e1	e0	e0	e1
Humidity sensitivity level	4	4	-	4	4	4	4	4
Configurable number of logic blocks	25920	25920	-	15360	25920	25920	18720	18720
Number of entries	960	960	-	960	1200	1200	960	960
Number of logical units	331776	331776	-	196608	331776	331776	239616	239616
Output times	960	960	-	960	1200	1200	960	960
organize	25920 CLBS	25920 CLBS	-	15360 CLBS	25920 CLBS	25920 CLBS	18720 CLBS	18720 CLBS
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	-	BGA	BGA	BGA	BGA	BGA
Encapsulate equivalent code	BGA1738,42X42,40	BGA1738,42X42,40	-	BGA1738,42X42,40	BGA1760,42X42,40	BGA1760,42X42,40	BGA1738,42X42,40	BGA1738,42X42,40
Package shape	SQUARE	SQUARE	-	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Peak Reflow Temperature (Celsius)	225	245	-	225	245	225	225	245
power supply	1,2.5 V	1,2.5 V	-	1,2.5 V	1,2.5 V	1,2.5 V	1,2.5 V	1,2.5 V
Programmable logic type	FPGA	FPGA	-	FPGA	FPGA	FPGA	FPGA	FPGA
Certification status	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	3.25 mm	3.25 mm	-	3.25 mm	3.5 mm	3.5 mm	3.25 mm	3.25 mm
Maximum supply voltage	1.05 V	1.05 V	-	1.05 V	1.05 V	1.05 V	1.05 V	1.05 V
Minimum supply voltage	0.95 V	0.95 V	-	0.95 V	0.95 V	0.95 V	0.95 V	0.95 V
Nominal supply voltage	1 V	1 V	-	1 V	1 V	1 V	1 V	1 V
surface mount	YES	YES	-	YES	YES	YES	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL	-	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn63Pb37)	Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)	-	Tin/Lead (Sn63Pb37)	Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)
Terminal form	BALL	BALL	-	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	-	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	-	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	30	30	-	30	30	30	30	30
width	42.5 mm	42.5 mm	-	42.5 mm	42.5 mm	42.5 mm	42.5 mm	42.5 mm

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