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IS61LV25616AL-10T-TR

Description
Standard SRAM, 256KX16, 10ns, CMOS, PDSO44,
Categorystorage    storage   
File Size310KB,16 Pages
ManufacturerIntegrated Silicon Solution ( ISSI )
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IS61LV25616AL-10T-TR Overview

Standard SRAM, 256KX16, 10ns, CMOS, PDSO44,

IS61LV25616AL-10T-TR Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIntegrated Silicon Solution ( ISSI )
Reach Compliance Codecompliant
Maximum access time10 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-G44
memory density4194304 bit
Memory IC TypeSTANDARD SRAM
memory width16
Number of terminals44
word count262144 words
character code256000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize256KX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP
Encapsulate equivalent codeTSOP44,.46,32
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Parallel/SerialPARALLEL
power supply3.3 V
Certification statusNot Qualified
Maximum standby current0.01 A
Minimum standby current2 V
Maximum slew rate0.09 mA
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationDUAL
Base Number Matches1
IS61LV25616AL
256K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
FEATURES
• High-speed access time:
— 10, 12 ns
• CMOS low power operation
• Low stand-by power:
— Less than 5 m
A
(typ.) CMOS stand-by
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Lead-free available
DECEMBER 2011
static RAM organized as 262,144 words by 16 bits. It is
fabricated using
ISSI
's high-performance CMOS technol-
ogy. This highly reliable process coupled with innovative
circuit design techniques, yields high-performance and low
power consumption devices.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be re-
duced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61LV25616AL is packaged in the JEDEC standard
44-pin 400-mil SOJ, 44-pin TSOP Type II, 44-pin LQFP
and 48-pin Mini BGA (8mm x 10mm).
DESCRIPTION
The
ISSI
IS61LV25616AL is a high-speed, 4,194,304-bit
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 16
MEMORY ARRAY
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. F
12/15/2011
1

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