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V385AGLFT

Description
IC xmitter 1b8t lvds vid 56tssop
Categorysemiconductor    Analog mixed-signal IC   
File Size88KB,8 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Environmental Compliance  
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IC xmitter 1b8t lvds vid 56tssop

V385A
8-B
IT
LVDS T
RANSMITTER FOR
V
IDEO
General Description
The V385A transmitter converts 28 bits of 3.3 V
CMOS/TTL into 4 Low Voltage Differential Signaling
(LVDS) data streams while the transmit clock input is
transmitted in parallel with the data streams over a fifth
LVDS link.
Compared to the V385, the V385A provides an
extended clock frequency range of 12-90 MHz, rather
than 20-85 MHz. Other performance improvements
have been incorporated as well.
The V385A can be programmed for rising edge or
falling edge clocks through pin R_FB.
Features
Extended clock frequency range of 12 to 90 MHz
Convert 28 bits of 3.3 V CMOS/TTL into 4 LVDS
streams
Up to 2.52 Gbps throughput or 315 Megabytes/sec
bandwidth
Pin Assignment
VCC
TxIN5
TxIN6
TxIN7
GND
TxIN8
TxIN9
TxIN10
VCC
TxIN11
TxIN12
TxIN13
GND
TxIN14
TxIN15
TxIN16
R_FB
TxIN17
TxIN18
TxIN19
GND
TxIN20
TxIN21
TxIN22
TxIN23
VCC
TxIN24
TxIN25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
TxIN4
TxIN3
TxIN2
GND
TxIN1
TxIN0
TxIN27
LVDS_GND
TxOUT0-
TxOUT0+
TxOUT1-
TxOUT1+
LVDS_VCC
LVDS_GND
TxOUT2-
TxOUT2+
TxCLKOUT-
TxCLKOUT+
TxOUT3-
TxOUT3+
LVDS_GND
PLL_GND
PLL_VCC
PLL_GND
PWRDWN
TxCLKIN
TxIN26
GND
Spread spectrum compatible
Supports SD, HD and VGA graphics applications
LVDS voltage swing of 350 mV for low EMI
On-chip PLL requires no external components
Single 3.3 V low-power CMOS design
Operating temperature of -10 to +70°C
Programmable rising or falling edge strobe
Power-down control function
Compatible with TIA/EIA-644 LVDS standards
Packaged in a 56-pin TSSOP (Pb free available)
Pin and function compatible with the National
DS90C385, TI SN65LVDS93 and THine
THC63LVDM83, but with extended clock frequency
and operating temperature range
Block Diagram
Red, Green, Blue
HSYNC
VSYNC
DATA ENABLE
CONTROL
TxOUT2-
R_FB
PWRDWN
CLOCK
PLL
TxCLKOUT-
TxOUT3+
TxOUT3-
TxCLKOUT+
TTL to
LVDS
TxOUT1-
TxOUT2+
24
TxOUT0+
TxOUT0-
TxOUT1+
56-pin TSSOP
V385A Datasheet
1
6/6/07
Revision 1.2
I DT • 2 0 6 4 S i l v e r C r e ek Va l l e y R o a d, S a n J os e , CA 9 5 1 3 8 • t e l ( 8 0 0 ) 3 4 5 - 7 0 1 5 • w w w. i dt . c o m

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