Simplifying System Integration
TM
73S12xxF
Software User Guide
September 14, 2009
Rev. 1.50
UG_12xxF_016
73S12xxF Software User Guide
UG_12xxF_016
© 2009 Teridian Semiconductor Corporation. All rights reserved.
Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation.
Simplifying System Integration is a trademark of Teridian Semiconductor Corporation.
Windows, Visual Basic, Visual Studio and Visual C/C++ are registered trademarks of Microsoft
Corporation.
Pentium is a registered trademark of Intel Corporation.
µVision is a registered trademark of Keil (an ARM
®
Company).
Linux is a registered trademark of Linus Torvalds.
MasterCard is a registered trademark of MasterCard Worldwide.
Visa is a registered trademark of Visa Inc.
All other trademarks are the property of their respective owners.
Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly
contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms
and Conditions. The company assumes no responsibility for any errors which may appear in this
document, reserves the right to change devices or specifications detailed herein at any time without
notice and does not make any commitment to update the information contained herein. Accordingly, the
reader is cautioned to verify that this document is current by comparing it to the latest version on
http://www.teridian.com or by checking with your sales representative.
Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com
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Table of Contents
1
Introduction ................................................................................................................................... 5
1.1 Acronyms ................................................................................................................................ 5
1.2 Use of this Document............................................................................................................... 6
1.3 Statement of Compliance ......................................................................................................... 6
Design Guide ................................................................................................................................. 7
2.1 Development Environment ...................................................................................................... 7
2.1.1 Hardware Requirements .............................................................................................. 7
2.1.2 Software Requirements ............................................................................................... 7
2.2 Software Build Environment ..................................................................................................... 8
2.2.1 Software Architecture .................................................................................................. 8
2.2.2 API/Library and Header Files ..................................................................................... 10
2.2.3 External Application ................................................................................................... 11
2.2.4 Embedded Application .............................................................................................. 11
2.2.5 Build Environment with the Serial Boot Loader .......................................................... 11
2.2.6 Build Environment with the USB DFU Boot Loader.................................................... 14
Testing Environment................................................................................................................... 17
3.1 EMV Level I Compliant Testing .............................................................................................. 17
3.2 CCID Testing ......................................................................................................................... 17
3.2.1 USB Testing: Microsoft HCT/DTM, and USB Command Verifier ................................ 17
3.2.2 Serial Testing ............................................................................................................ 18
Design Reference ........................................................................................................................ 19
4.1 Memory Map .......................................................................................................................... 19
4.1.1 Program Memory....................................................................................................... 19
4.1.2 External Data Memory ............................................................................................... 20
4.1.3 Internal Data Memory ................................................................................................ 20
4.2 Low-level API ......................................................................................................................... 20
4.2.1 Keyboard Driver API – Available with all 73S12xxF Devices ....................................... 21
4.2.2 LCD Driver API – Available with all 73S12xxF Devices .............................................. 23
4.2.3 LED Driver API – Available with all 73S12xxF Devices............................................... 24
4.2.4 Real Time Clock API - Available with the 68-pin 73S12xxF ....................................... 26
4.2.5 Smart Card Interface Driver API – Available with all 73S12xxF Devices ..................... 30
4.2.6 SERIAL (RS232) Driver API – Available with all 73S12xxF Devices ........................... 39
4.2.7 USB API – Available with 64K Flash version of the 73S12xxF ................................... 42
4.2.8 Clock Generator Circuit API – Available with all 73S12xxF Devices ........................... 51
4.2.9 Power Management API – Available with all 73S12xxF Devices ................................ 52
4.2.10 Analog Threshold Management Driver API – Available with all 73S12xxF Devices ..... 53
4.2.11 Event Management API – Available with all 73S12xxF Devices ................................. 55
4.2.12 Timers API – Available with all 73S12xxF Devices ..................................................... 57
4.2.13 User IO API – Available with all 73S12xxF Devices ................................................... 58
4.2.14 External Interrupts API – Available with all 73S12xxF Devices ................................... 60
4.2.15 Special Function Register API – Available with all 73S12xxF Devices ........................ 61
4.2.16 Flash/Memory API – Available with all 73S12xxF Devices.......................................... 63
4.2.17 Boot Loader and Passcode Management – Available with the LAPI-*BL.lib Only ....... 67
4.2.18 Security Mode Management - Available with the LAPI-*BL.lib Only........................... 69
4.2.19 Other Miscellaneous API Calls – Available with all 73S12xxF Devices ....................... 71
4.3 High-Level API ....................................................................................................................... 72
4.3.1 Smart Card Control ................................................................................................... 72
4.4 Flash Programming ............................................................................................................... 85
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4.5 Test Tools and Certification/compliance Tests ........................................................................ 85
4.5.1 EMV LEVEL I Certification Tests .............................................................................. 86
4.5.1.1 EMV Test Mode..................................................................................... 86
4.5.1.2 MasterCard Loopback Test .................................................................... 87
4.5.1.3 VISA-1 Loopback Test ............................................................................ 90
4.5.2
5
6
VISA-2 Loopback Test .............................................................................................. 91
Related Documentation .............................................................................................................. 92
Contact Information .................................................................................................................... 92
Revision History .................................................................................................................................. 93
Figures
Figure 1: Software Architecture Diagram.................................................................................................. 9
Figure 2: Device Options for Building with the Boot Loader .................................................................... 12
Figure 3: Target Options for Building with the Boot Loader .................................................................... 13
Figure 4: C51 Options for Building with the Boot Loader........................................................................ 13
Figure 5: Target Options for Building with the DFU Boot Loader ............................................................ 15
Figure 6: C51 Options for Building with the Boot Loader........................................................................ 16
Figure 7: Memory Layout ....................................................................................................................... 19
Figure 8: Smart Card Rx/Tx Timing........................................................................................................ 31
Figure 9: Boot Loader Scenario ............................................................................................................. 67
Figure 10: FLASH Download and Programming Process....................................................................... 68
Figure 11: EMV PSE Test Flow Chart .................................................................................................... 87
Figure 12: MCI Test Flow Chart with PTS/PPS ...................................................................................... 88
Figure 13: MCI Test Flow Chart without PTS/PPS ................................................................................. 89
Figure 14: VISA-1 Loopback Test Flow Chart ........................................................................................ 90
Figure 15: VISA-2 Loopback Test Flow Chart ........................................................................................ 91
Tables
Table 1: Upper 1 KB External Data Memory layout ................................................................................ 20
Table 2: IRAM Special Function Register Map ....................................................................................... 20
Table 3: Interrupt Sources and Priority Level.......................................................................................... 21
Table 4: Clock Speeds and Baud Rates Supported ............................................................................... 51
Table 5: Security Mode Actions Allowed ................................................................................................ 70
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1 Introduction
The Teridian Semiconductor Corporation 73S12xxF single-chip Smart Card Terminal Controllers consist
of the 73S1209F, 73S1210F, 73S1215F and 73S1217F. These System-on-Chip devices provide the
functions necessary to build a low-cost smart card terminal.
The 73S12xxF Evaluation Board allows development of an embedded application in conjunction with an
In-Circuit Emulator (ICE). An application can be programmed in either ANSI C or 80515 assembly
language using this evaluation board.
Teridian provides a development Toolkit that includes a set of libraries (Application Programming
Interface or API). The API is written in ANSI C to control all the features present on the evaluation
boards. These libraries include functions to manage the low-level 80515 core functions such as memory,
clock, power modes, interrupts; and high-level functions such as the Liquid Crystal Display (LCD),
keyboard, Real-Time Clock (RTC), smart card interfaces, Universal Serial Bus (USB)/Serial interfaces and
I/Os. These APIs reduce development time dramatically, since they allow the developer to focus on
developing the application without dealing with the low-level layer such as hardware control, timing, etc.
This document describes the Toolkit’s hierarchical layers and how to use them.
Certain function blocks (such as USB and RTC) are not available on all 73S12xxF devices. As a result,
the related APIs can not be used with some ICs. Refer to the data sheets for further details.
This document applies to the following components:
•
•
•
•
•
LAPI Version 4.00 (DFU), LAPI Version 3.30 (BL), LAPI Version 2.30 (non-BL)
HAPI Version 4.00 (DFU), HAPI Version 3.30 (BL), HAPI Version 2.40 (non-BL)
Serial Pseudo-CCID Application Version 3.1
USB CCID Application Version 2.1 (DFU), USB CCID Application Version 1.5 (non-DFU)
Devices: 1215A05, 1217A06 and 1210/1209A02
1.1
Acronyms
Application Protocol Data Unit
Application Programming Interface
Answer To Reset
Boot Loader
Integrated Circuit Card Interface Device
Communication Port
Device Firmware Upgrade
Development ToolKit
Device Test Manager
Euro, MasterCard
®
, Visa
®
High-level API
Hardware Compatibility Test
Integrated Circuit Card
International Standards Organization
In-System Programming
Japan IC Card System Application council
Low-level API
Low-level API exerciser
Liquid Crystal Display
Non Boot Loader
Personal Computer
Personal Indentification
Random Access Memory
Read Only Memory
5
APDU
API
ATR
BL
CCID
COM
DFU
DTK
DTM
EMV
HAPI
HCT
ICC
ISO
ISP
JICSAP
LAPI
LAPIE
LCD
Non-BL
PC
PIN
RAM
ROM
Rev. 1.50
PCB Design
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