IDT71V3548S datasheet, PDF - EEWORLD Datasheet

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IDT71V3548S: Description256k x 18 3.3V synchronous zbt sram 3.3V I/O, burst counter pipelined outputs; File Size490KB，26 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT71V3548S Overview

256k x 18 3.3V synchronous zbt sram 3.3V I/O, burst counter pipelined outputs

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256K x 18

3.3V Synchronous ZBT SRAM

3.3V I/O, Burst Counter

Pipelined Outputs

IDT71V3548S

IDT71V3548SA

Features

256K x 18 memory configurations

Supports high performance system speed - 133 MHz

(4.2 ns Clock-to-Data Access)

ZBT

Feature - No dead cycles between write and read

cycles

Internally synchronized output buffer enable eliminates the

need to control

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW

) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%), 3.3V I/O Supply (V

DDQ)

Optional Boundary Scan JTAG Interface (IEEE 1149.1

compliant)

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA)

Description

The IDT71V3548 are 3.3V high-speed 4,718,592-bit (4.5 Megabit)

synchronous SRAMS. They are designed to eliminate dead bus

cycles when turning the bus around between reads and writes, or

writes and reads. Thus, they have been given the name ZBT

, or

Zero Bus Turnaround.

Address and control signals are applied to the SRAM during one

clock cycle, and two cycles later the associated data cycle occurs, be it

read or write.

The IDT71V3548 contain data I/O, address and control signal

registers. Output enable is the only asynchronous signal and can be used

to disable the outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V3548

to be suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is high and the internal device registers will hold

their previous values.

There are three chip enable pins (CE

, CE

) that allow the user

to deselect the device when desired. If any one of these three are not

asserted when ADV/LD is low, no new memory operation can be

initiated. However, any pending data transfers (reads or writes) will be

completed. The data bus will tri-state two cycles after chip is deselected

or a write is initiated.

The IDT71V3548 has an on-chip burst counter. In the burst

mode, the IDT71V3548 can provide four cycles of data for a single address

presented to the SRAM. The order of the burst sequence is defined by the

LBO

input pin. The

LBO

pin selects between linear and interleaved burst

sequence. The ADV/LD signal is used to load a new external address

(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =

HIGH).

The IDT71V3548 SRAMs utilize IDT's latest high-performance CMOS

process and are packaged in a JEDEC standard 14mm x 20mm 100- pin

plastic thin quad flatpack (TQFP) as well as a 119 ball grid array (BGA)

and 165 fine pitch ball grid array (fBGA).

Input

Output

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

Static

Synchronous

N/A

Synchronous

Asynchronous

Synchronous

Static

5296 tbl 01

Pin Description Summary

-A

, CE

R/W

CEN

CLK

ADV/LD

LBO

TMS

TDI

TCK

TDO

TRST

I/O

-I/O

, I/O

-I/O

, V

DDQ

Address Inputs

Chip Enables

Output Enable

Read/Write Signal

Clock Enable

Individual Byte Write Selects

Clock

Advance burst addre ss / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Test Clock

Test Data Output

JTAG Reset (Optional)

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

MAY 2002

DSC-5296/03

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