fpga - field programmable gate array 2M system gates
| Parameter Name | Attribute value |
| Is it Rohs certified? | incompatible |
| Maker | Actel |
| package instruction | 1 MM PITCH, FBGA-1152 |
| Reach Compliance Code | compliant |
| Other features | 2000000 SYSTEM GATES AVAILABLE |
| maximum clock frequency | 763 MHz |
| Combined latency of CLB-Max | 0.84 ns |
| JESD-30 code | S-PBGA-B1152 |
| JESD-609 code | e0 |
| length | 35 mm |
| Humidity sensitivity level | 3 |
| Configurable number of logic blocks | 21504 |
| Equivalent number of gates | 1060000 |
| Number of entries | 684 |
| Number of logical units | 32256 |
| Output times | 684 |
| Number of terminals | 1152 |
| Maximum operating temperature | 70 °C |
| Minimum operating temperature | |
| organize | 21504 CLBS, 1060000 GATES |
| Package body material | PLASTIC/EPOXY |
| encapsulated code | BGA |
| Encapsulate equivalent code | BGA1152,34X34,40 |
| Package shape | SQUARE |
| Package form | GRID ARRAY |
| Peak Reflow Temperature (Celsius) | 225 |
| power supply | 1.5,1.5/3.3,2.5/3.3 V |
| Programmable logic type | FIELD PROGRAMMABLE GATE ARRAY |
| Certification status | Not Qualified |
| Maximum seat height | 2.44 mm |
| Maximum supply voltage | 1.575 V |
| Minimum supply voltage | 1.425 V |
| Nominal supply voltage | 1.5 V |
| surface mount | YES |
| technology | CMOS |
| Temperature level | COMMERCIAL |
| Terminal surface | Tin/Lead (Sn/Pb) |
| Terminal form | BALL |
| Terminal pitch | 1 mm |
| Terminal location | BOTTOM |
| Maximum time at peak reflow temperature | 30 |
| width | 35 mm |
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