3V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI &
QUAD I/O QPI DTR INTERFACE
DATA SHEET
IS25LP128/064
128/64Mb
3V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI &
QUAD I/O QPI DTR INTERFACE
FEATURES
Industry Standard Serial Interface
-
IS25LP128: 128Mbit/16Mbyte
-
IS25LP064: 64Mbit/8Mbyte
-
256 bytes per Programmable Page
-
Supports standard SPI, Fast, Dual, Dual
I/O, Quad I/O, SPI DTR, Dual I/O DTR,
Quad I/O DTR, and QPI
-
Double Transfer Rate (DTR) option
-
Supports Serial Flash Discoverable
Parameters (SFDP)
High Performance Serial Flash (SPI)
-
133Mhz Fast Read at Vcc=2.7V to 3.6V
-
104Mhz Fast Read at Vcc=2.3V to 3.6V
-
532MHz equivalent at QPI operation
-
50MHz Normal Read
-
DTR (Dual Transfer Rate) up to 66MHz
-
Selectable dummy cycles
-
Configurable drive strength
-
Supports SPI Modes 0 and 3
-
More than 100,000 erase/program cycles
-
More than 20-year data retention
Flexible & Efficient Memory Architecture
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Chip Erase with Uniform Sector/Block
Erase (4/32/64 Kbyte)
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Program 1 to 256 bytes per page
-
Program/Erase Suspend & Resume
Efficient Read and Program modes
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Low Instruction Overhead Operations
-
Continuous Read 8/16/32/64-Byte Burst
Wrap
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Selectable burst length
-
QPI for reduced instruction overhead
Low Power with Wide Temp. Ranges
-
Single 2.3V to 3.6V Voltage Supply
-
5 mA Active Read Current
-
10 µA Standby Current
-
5 µA Deep Power Down
-
Temp Grades:
Extended: -40°C to +105°C
(1)
Extended+: -40°C to +125°C
Auto Grade: up to +125°C
Note:
1.
Extended+ should not be used for Automotive.
Advanced Security Protection
-
Software and Hardware Write Protection
-
Power Supply lock protect
-
4x256-Byte dedicated security area
with OTP user-lockable bits
-
128 bit Unique ID for each device (Call
Factory)
Industry Standard Pin-out & Packages
-
B = 8-pin SOIC 208mil
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F = 8-pin VSOP 208mil
-
K = 8-contact WSON 6x5mm
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L = 8-contact WSON 8x6mm
-
M = 16-pin SOIC 300mil
-
G= 24-ball TFBGA 6x8mm 4x6
-
H =
24-ball TFBGA 6x8mm 5x5
(Call Factory)
-
KGD (Call Factory)
(1)
Notes:
1. Call Factory for other package options available
Integrated Silicon Solution, Inc.- www.issi.com
Rev. K1
03/28/2016
2
IS25LP128/064
GENERAL DESCRIPTION
The IS25LP128/064 Serial Flash memory offers a versatile storage solution with high flexibility and performance
in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash are for systems that require
limited space, a low pin count, and low power consumption. The device is accessed through a 4-wire SPI
Interface consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable
(CE#) pins, which can also be configured to serve as multi-I/O (see pin descriptions).
The device supports Dual and Quad I/O as well as standard and Dual Output SPI. Clock frequencies of up to
133MHz allow for equivalent clock rates of up to 532MHz (133MHz x 4) which equates to 66Mbytes/s of data
throughput. The IS25xP series of Flash adds support for DTR (Double Transfer Rate) commands that transfer
addresses and read data on both edges of the clock. These transfer rates can outperform 16-bit Parallel Flash
memories allowing for efficient memory access to support XIP (execute in place) operation.
The memory array is organized into programmable pages of 256-bytes. This family supports page program
mode where 1 to 256 bytes of data are programmed in a single command. QPI (Quad Peripheral Interface)
supports 2-cycle instruction further reducing instruction times. Pages can be erased in groups of 4Kbyte
sectors, 32Kbyte blocks, 64Kbyte blocks, and/or the entire chip. The uniform sector and block architecture
allows for a high degree of flexibility so that the device can be utilized for a broad variety of applications
requiring solid data retention.
GLOSSARY
Standard SPI
In this operation, a 4-wire SPI Interface is utilized, consisting of Serial Data Input (SI), Serial Data Output (SO),
Serial Clock (SCK), and Chip Enable (CE#) pins. Instructions are sent via the SI pin to encode instructions,
addresses, or input data to the device on the rising edge of SCK. The SO pin is used to read data or to check the
status of the device. This device supports SPI bus operation modes (0,0) and (1,1).
Multi I/O SPI
Multi-I/O operation utilizes an enhanced SPI protocol to allow the device to function with Dual Output, Dual Input
and Output, Quad Output, and Quad Input and Output capability. Executing these instructions through SPI
mode will achieve double or quadruple the transfer bandwidth for READ and PROGRAM operations.
QPI
The device supports Quad Peripheral Interface (QPI) operations only when the device is switched from
Standard/Dual/Quad SPI mode to QPI mode using the enter QPI (35h) instruction. The typical SPI protocol
requires that the byte-long instruction code being shifted into the device only via SI pin in eight serial clocks. The
QPI mode utilizes all four I/O pins to input the instruction code thus requiring only two serial clocks. This can
significantly reduce the SPI instruction overhead and improve system performance. Only QPI mode or
SPI/Dual/Quad mode can be active at any given time. Enter QPI (35h) and Exit QPI (F5h) instructions are used
to switch between these two modes, regardless of the non-volatile Quad Enable (QE) bit status in the Status
Register. Power Reset or Hardware/Software Reset will return the device into the standard SPI mode. SI and
SO pins become bidirectional I/O0 and I/O1, and WP# and HOLD# pins become I/O2 and I/O3 respectively
during QPI mode.
DTR
In addition to SPI and QPI features, the device also supports Fast READ DTR operation, which allows high data
throughput while running at lower clock frequencies. DTR READ mode uses both rising and falling edges of the
clock to drive output, resulting in reducing input and output cycles by half.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. K1
03/28/2016
3
IS25LP128/064
TABLE OF CONTENTS
FEATURES .......................................................................................................................................................... 2
GENERAL DESCRIPTION .................................................................................................................................. 3
TABLE OF CONTENTS ....................................................................................................................................... 4
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