935319036557 datasheet, PDF - EEWORLD Datasheet

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935319036557: DescriptionRISC Microcontroller; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，55 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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935319036557 Overview

RISC Microcontroller

935319036557 Parametric

Parameter Name	Attribute value
Maker	NXP
package instruction	LQFP,
Reach Compliance Code	unknown
Has ADC	YES
Address bus width
bit size	32
maximum clock frequency	60 MHz
DMA channel	YES
External data bus width
length	20 mm
Number of I/O lines	73
Number of terminals	112
PWM channel	YES
encapsulated code	LQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE
speed	60 MHz
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
width	20 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC
Base Number Matches	1

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Freescale Semiconductor

Data Sheet: Technical Data

Document Number: MCF52235

Rev. 10, 3/2011

MCF52235

MCF52235 ColdFire

Microcontroller Data Sheet

Supports MCF52230, MCF52231,

MCF52232, MCF52233, MCF52234,

MCF52235, and MCF52236

The MCF52235 is a member of the ColdFire

family of

reduced instruction set computing (RISC) microcontrollers.

This document provides an overview of the MCF52235

microcontroller family, focusing on its highly integrated and

diverse feature set.

This 32-bit device is based on the Version 2 ColdFire core

operating at a frequency up to 60 MHz, offering high

performance and low power consumption. On-chip memories

connected tightly to the processor core include up to 256

Kbytes of Flash and 32 Kbytes of static random access

memory (SRAM). On-chip modules include:

• V2 ColdFire core providing 56 Dhrystone 2.1 MIPS @ 60

MHz executing out of on-chip Flash memory using

enhanced multiply accumulate (EMAC) and hardware

divider

• Enhanced Multiply Accumulate Unit (EMAC) and

hardware divide module

• Cryptographic Acceleration Unit (CAU) coprocessor

• Fast Ethernet Controller (FEC)

• On-chip Ethernet Transceiver (EPHY)

• FlexCAN controller area network (CAN) module

• Three universal asynchronous/synchronous

receiver/transmitters (UARTs)

• Inter-integrated circuit (I

C™) bus controller

• Queued serial peripheral interface (QSPI) module

• Eight-channel 10- or 12-bit fast analog-to-digital converter

(ADC)

• Four channel direct memory access (DMA) controller

• Four 32-bit input capture/output compare timers with

DMA support (DTIM)

• Four-channel general-purpose timer (GPT) capable of

input capture/output compare, pulse width modulation

(PWM) and pulse accumulation

• Eight/Four-channel 8/16-bit pulse width modulation timers

(two adjacent 8-bit PWMs can be concatenated to form a

single 16-bit timer)

•

LQFP-80

14mm x 14mm

LQFP-112

20mm_x_20mm

MAPBGA-121

12mm_x_12mm

Two 16-bit periodic interrupt timers (PITs)

Real-time clock (RTC) module

Programmable software watchdog timer

Two interrupt controllers providing every peripheral with a

unique selectable-priority interrupt vector plus seven

external interrupts with fixed levels/priorities

• Clock module with support for crystal or external oscillator

and integrated phase-locked loop (PLL)

• Test access/debug port (JTAG, BDM)

Freescale reserves the right to change the detail specifications as may be required to permit

improvements in the design of its products.

Table of Contents

MCF52235 Family Configurations . . . . . . . . . . . . . . . . . . . . . .3

1.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.3 Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

1.4 PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . .22

1.5 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

1.6 External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . .22

1.7 Queued Serial Peripheral Interface (QSPI). . . . . . . . . .23

1.8 Fast Ethernet Controller EPHY Signals . . . . . . . . . . . .23

1.9 I

C I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

1.10 UART Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . .24

1.11 DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

1.12 ADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

1.13 General Purpose Timer Signals . . . . . . . . . . . . . . . . . .25

1.14 Pulse Width Modulator Signals . . . . . . . . . . . . . . . . . . .25

1.15 Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . .25

1.16 EzPort Signal Descriptions . . . . . . . . . . . . . . . . . . . . . .27

1.17 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . .27

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

2.2 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

2.3 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .32

2.4 Phase Lock Loop Electrical Specifications . . . . . . . . . .33

2.5 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . .35

2.6 Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

2.7 I

C Input/Output Timing Specifications . . . . . . . . . . . . .36

2.8 EPHY Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

2.9 Analog-to-Digital Converter (ADC) Parameters . . . . . .40

2.10 DMA Timers Timing Specifications . . . . . . . . . . . . . . . .42

2.11 EzPort Electrical Specifications . . . . . . . . . . . . . . . . . .42

2.12 QSPI Electrical Specifications. . . . . . . . . . . . . . . . . . . .43

2.13 JTAG and Boundary Scan Timing. . . . . . . . . . . . . . . . .44

2.14 Debug AC Timing Specifications. . . . . . . . . . . . . . . . . .46

Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .47

3.1 80-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .47

3.2 112-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . .48

3.3 121 MAPBGA Package. . . . . . . . . . . . . . . . . . . . . . . . .51

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Figure 14.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . .

Figure 15.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . .

Figure 16.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . .

Figure 17.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 18.Real-Time Trace AC Timing . . . . . . . . . . . . . . . . . . . .

Figure 19.BDM Serial Port AC Timing . . . . . . . . . . . . . . . . . . . .

List of Tables

Table 1. MCF52235 Family Configurations . . . . . . . . . . . . . . . . . 3

Table 2. Orderable Part Number Summary. . . . . . . . . . . . . . . . 13

Table 3. Pin Functions by Primary and Alternate Purpose . . . . 17

Table 4. Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 5. PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 6. Mode Selection Signals . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 7. External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . 22

Table 8. Queued Serial Peripheral Interface (QSPI) Signals. . . 23

Table 9. Fast Ethernet Controller (FEC) Signals . . . . . . . . . . . . 23

Table 10.I

C I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 11.UART Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 12.DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 13.ADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 14.GPT Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 15.PWM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 16.Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 17.EzPort Signal Descriptions . . . . . . . . . . . . . . . . . . . . . 27

Table 18.Power and Ground Pins. . . . . . . . . . . . . . . . . . . . . . . . 27

Table 19.Absolute Maximum Ratings, . . . . . . . . . . . . . . . . . . . 29

Table 20.Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 30

Table 21.ESD Protection Characteristics . . . . . . . . . . . . . . . . . . 31

Table 22.DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . 32

Table 23.Active Current Consumption Specifications. . . . . . . . . 33

Table 24.Current Consumption Specifications in

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 25.PLL Electrical Specifications . . . . . . . . . . . . . . . . . . . . 33

Table 26.GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 27.Reset and Configuration Override Timing . . . . . . . . . . 35

Table 28.I

C Input Timing Specifications between

I2C_SCL and I2C_SDA . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 29. I

C Output Timing Specifications between

I2C_SCL and I2C_SDA . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 30.EPHY Timing Parameters . . . . . . . . . . . . . . . . . . . . . . 38

Table 31.10BASE-T SQE (Heartbeat) Timing Parameters . . . . 38

Table 32.10BASE-T Jab and Unjab Timing Parameters . . . . . . 39

Table 33.10BASE-T Transceiver Characteristics . . . . . . . . . . . . 40

Table 34.100BASE-TX Transceiver Characteristics . . . . . . . . . . 40

Table 35.ADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 36.Timer Module AC Timing Specifications . . . . . . . . . . . 42

Table 37.EzPort Electrical Specifications . . . . . . . . . . . . . . . . . . 42

Table 38.QSPI Modules AC Timing Specifications. . . . . . . . . . . 43

Table 39.JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 44

Table 40.Debug AC Timing Specification . . . . . . . . . . . . . . . . . . 46

Table 41.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

List of Figures

Figure 1. MCF52235 Block Diagram . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. 80-pin LQFP Pin Assignments . . . . . . . . . . . . . . . . . . 14

Figure 3. 112-pin LQFP Pin Assignments . . . . . . . . . . . . . . . . . 15

Figure 4. 121 MAPBGA Pin Assignments . . . . . . . . . . . . . . . . . 16

Figure 5. Suggested Connection Scheme for Power and Ground 28

Figure 6. GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 7. RSTI and Configuration Override Timing . . . . . . . . . . 36

Figure 8. I

C Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . 37

Figure 9. EPHY Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 10.10BASE-T SQE (Heartbeat) Timing . . . . . . . . . . . . . 39

Figure 11.10BASE-T Jab and Unjab Timing . . . . . . . . . . . . . . . 39

Figure 12.Equivalent Circuit for A/D Loading. . . . . . . . . . . . . . . 42

Figure 13.QSPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

Freescale Semiconductor

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