High Speed Super Low Power SRAM
256K-Word By 8 Bit
CS18LV20483
Revision History
Rev. No.
1.0
History
Initial issue
Issue Date
Jan.26,2005
Remark
1
Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
256K-Word By 8 Bit
CS18LV20483
GENERAL DESCRIPTION
The CS18LV20483 is a high performance, high speed, and super low power CMOS Static
Random Access Memory organized as 262,144 words by 8 bits and operates from a wide range of
2.7 to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of 0.50uA and maximum
access time of 55/70ns in 3.0V operation. Easy memory expansion is provided by an active LOW
chip enable inputs (/CE1,CE2) and active LOW output enable (/OE) and three-state output drivers.
The CS18LV20483 has an automatic power down feature, reducing the power consumption
significantly when chip is deselected. The CS18LV20483 is available in JEDEC standard 32-pin
sTSOP (8x13.4 mm), TSOP (8x20mm), TSOP (II) (400mil) and SOP (450 mil) packages.
.
FEATURES
Low operation voltage : 2.7 ~ 3.6V
Ultra low power consumption : 2mA＠1MHz (Max.) operating current
0.50 uA (Typ.) CMOS standby current
High speed access time : 55/70ns (Max.) at Vcc = 3.0V.
Automatic power down when chip is deselected.
Three state outputs and TTL compatible
Data retention supply voltage as low as 1.5V.
Easy expansion with /CE and /OE options.
Product Family
Product Family
Operating
Temp
Vcc. Range
Speed (ns) Standby (Typ.) Package Type
32 SOP
0~70
o
C
0.50 uA
(Vcc = 3.0V)
32 STSOP
32 TSOP
32 TSOP (II)
Dice
32 SOP
-40~85
o
C
0.8 uA
(Vcc= 3.0V)
32 STSOP
32 TSOP
32 TSOP (II)
Dice
2
Rev. 1.0
2.7~3.6
55/70
CS18LV20483
2.7~3.6
55/70
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
256K-Word By 8 Bit
CS18LV20483
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
3
Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
256K-Word By 8 Bit
CS18LV20483
PIN DESCRIPTIONS
Type
Name
A0 – A17
Input
Address inputs for selecting one of the 262,144 x 8 bit words in the RAM
/CE1 is active LOW and CE2 is active HIGH. Both chip enables must be
active when data read from or write to the device. If either chip enable is
/CE1, CE2
Input
not active, the device is deselected and in a standby power down mode.
The DQ pins will be in high impedance state when the device is
deselected.
The Write enable input is active LOW. It controls read and write
/WE
Input
operations. With the chip selected, when /WE is HIGH and /OE is LOW,
output data will be present on the DQ pins, when /WE is LOW, the data
present on the DQ pins will be written into the selected memory location.
The output enable input is active LOW. If the output enable is active
/OE
Input
while the chip is selected and the write enable is inactive, data will be
present on the DQ pins and they will be enabled. The DQ pins will be in
the high impedance state when /OE is inactive.
DQ0~DQ7
Vcc
Gnd
NC
I/O
Power
Power
These 8 bi-directional ports are used to read data from or write data into
the RAM.
Power Supply
Ground
No connection
Function
TRUTH TABLE
MODE
Standby
X
Output
Disabled
Read
Write
L
L
L
/CE1
H
CE2
X
L
H
H
H
/WE
X
X
H
H
L
/OE
X
High Z
L
H
L
X
High Z
D
OUT
D
IN
I
CC
I
CC
I
CC
I
CCSB
, I
CCSB1
DQ0~7
Vcc Current
4
Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
256K-Word By 8 Bit
CS18LV20483
Rating
-0.5 to Vcc+0.5
-40 to +125
-60 to +150
1.0
25
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
V
TERM
T
BIAS
T
STG
P
T
I
OUT
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Unit
V
O
O
C
C
W
mA
1.
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0~70
o
C
-40~85
o
C
Vcc
2.7V ~ 3.6V
2.7V ~ 3.6V
1. Overshoot : Vcc +2.0V in case of pulse width
≦20ns.
2. Undershoot : - 2.0V in case of pulse width
≦20ns.
3. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE
(1)
(TA = 25
o
C, f =1.0 MHz)
Symbol
C
IN
C
DQ
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
V
IN
=0V
V
I/O
=0V
MAX.
6
8
Unit
pF
pF
1. This parameter is guaranteed and not tested.
5
Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
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