V916732J24QAJZ-D3 datasheet, PDF

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V916732J24QAJZ-D3: DescriptionDDR DRAM Module, 32MX64, 0.6ns, CMOS, PDMA240; Categorystorage storage; File Size134KB，15 Pages; ManufacturerProMOS Technologies Inc; Environmental Compliance

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V916732J24QAJZ-D3 Overview

DDR DRAM Module, 32MX64, 0.6ns, CMOS, PDMA240

V916732J24QAJZ-D3 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	ProMOS Technologies Inc
Reach Compliance Code	compliant
Maximum access time	0.6 ns
Maximum clock frequency (fCLK)	200 MHz
I/O type	COMMON
JESD-30 code	R-PDMA-N240
JESD-609 code	e3
memory density	2147483648 bit
Memory IC Type	DDR DRAM MODULE
memory width	64
Number of terminals	240
word count	33554432 words
character code	32000000
Maximum operating temperature	85 °C
Minimum operating temperature
organize	32MX64
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	DIMM
Encapsulate equivalent code	DIMM240,40
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.8 V
Certification status	Not Qualified
refresh cycle	8192
Maximum standby current	0.02 A
Maximum slew rate	1.12 mA
Nominal supply voltage (Vsup)	1.8 V
surface mount	NO
technology	CMOS
Temperature level	OTHER
Terminal form	NO LEAD
Terminal pitch	1 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Base Number Matches	1

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V916732J24QA

32M x 64 HIGH PERFORMANCE

UNBUFFERED DDR2 SDRAM MODULE

Features

• 240-pin, unbuffered dual in-line memory module

• JEDEC standard 1.8V + 0.1V power supply

• VDDQ=1.8V + 0.1V

• Fast data transfer rate: PC2-3200, PC2-4200, or

PC2-5300

• Programmable CAS Latency(CL): 3, 4, 5

• Programmable Additive Latency(AL): 0, 1, 2, 3

and 4

• Write Latency(WL)=Read Latency(RL)-1

• Programmble burst lengths: 4 or 8

• Differential data strobe (DQS, DQS#)

(Single ended data strobe option)

• On-die termination (ODT)

• Adjustable data-output drive strength

• 64ms, 8192-cycle refresh

• Serial Presence Detect (SPD) with EEPROM

•

Description

The V916732J24QA memory module is orga-

nized as 33,554,432 x 64 bits in a 240 pin memory

module. The 32M x 64 memory module uses 4

ProMOS 32M x 16 DDR2 SDRAMs. The x64 mod-

ules are ideal for use in high performance computer

systems where increased memory density and fast

access times are required.

Speed Grade

DDR2-400

PC2-3200 (D3)

Bandwith@CL=3

Bandwith@CL=4

Bandwith@CL=5

CL-tRCD-tRP

400

3-3-3

DDR2-533

PC2-4200 (E4)

400

533

4-4-4

DDR2-667

PC2-5300 (F5)

400

533

667

5-5-5

Units

Mbps

tCK

240-pin DDR2 Unbuffered DIMM

V916732J24QA Rev 1.0 March 2005

ProMOS TECHNOLOGIES

Pin Description

Symbol

CK0-CK2

CK0#-CK2#

CKE0-CKE1

Input

Type

Input

Function

V916732J24QA

CK and CK# are differential clock inputs. All the SDRAM addr/cntl inputs are sampled on the crossing

of positive edge of CK and negative edge of CK#. Output (read) data is reference to the crossing of

CK and CK# (Both directions of crossing)

Activates the SDRAM CK signal when high and deactivates the CK Signal When low. By deactivat-

ing the clocks, CKE low initiates the Powe Down mode, or the Self-Refresh mode

Enables the associated SDRAM command decoder when low and disables the command decoder

when high. When the command decoder is disbled, new command are ignored but previous opera-

tions continue. This signal provides for external rank selection on systems with multiple ranks

RAS#, CAS#, WE# (ALONG WITH CS#) define the command being entered.

When high, termination resistance is enabled for all DQ, DQ# and DM pins, assuming the function is

enabled in the Extended Mode Register Set (EMRS).

Reference voltage for SSTL 18 inputs.

Power supply for the DDR II SDRAM output buffers to provide improved noise immunity. For all cur-

rent DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins.

Selects which SDRAM BANK of four is activated.

During a Bank Activate command cycle, Address input defines the row address (RA0-RA13)

During a Read or Write command cycle, Address input defines the colum address, In addition to the

column address, AP is used to invoke autoprecharge operation at the end of the burst read or write

cycle. If AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If

AP is low, autoprecharge is disbled. During a precharge command cycle, AP is used in conjunction

with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks will be precharged

regardless of the state of BA0, BA1. If AP is low, BA0, BA1are used to define which bank to pre-

charge.

Data and Check Bit Input/Output pins.

DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident

with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins

are input only, the DM loading matches the DQ and DQS loading.

Power and ground for DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to

DDQ

planes on these modules.

Data strobe for input and output data. its edge-aligned with read data, center aligned with write data.

DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command.

These signals and tied at the system planar to either V

or V

to configure the serial SPD EER-

POM address range.

This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be

connected from the SDA bus line to VDD to act as a pullup on the system board.

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected

from the SCL bus time to VDD to act as a pullup onthe system board.

Power supply for SPD EEPROM. This supply is separate from the V

DDQ

power plane.

EEPROM supply is operable from 1.7V to 3.6V.

S0#- S1#

RAS#, CAS#, WE#

ODT0-ODT1

REF

DDQ

BA0-BA1

Input

Supply

Input

A0-A13

Input

DQ0-DQ63

CB0-CB7

DM0-DM8

In/Out

Input

DQS0-DQS8

DQS0#-DQS8#

SA0-SA2

SDA

SCL

SPD

Supply

In/Out

Input

In/Out

Input

Supply

V916732J24QA Rev 1.0 March 2005

V916732J24QAJZ-D3 Related Products

	V916732J24QAJZ-D3	V916732J24QAJZ-F5	V916732J24QAFX-F5	V916732J24QAJZ-E4
Description	DDR DRAM Module, 32MX64, 0.6ns, CMOS, PDMA240	DDR DRAM Module, 32MX64, 0.45ns, CMOS, PDMA240	DDR DRAM Module, 32MX64, 0.45ns, CMOS, PDMA240	DDR DRAM Module, 32MX64, 0.5ns, CMOS, PDMA240
Is it lead-free?	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to
Maker	ProMOS Technologies Inc	ProMOS Technologies Inc	ProMOS Technologies Inc	ProMOS Technologies Inc
Reach Compliance Code	compliant	compliant	compliant	compliant
Maximum access time	0.6 ns	0.45 ns	0.45 ns	0.5 ns
Maximum clock frequency (fCLK)	200 MHz	333 MHz	333 MHz	266 MHz
I/O type	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-PDMA-N240	R-PDMA-N240	R-PDMA-N240	R-PDMA-N240
JESD-609 code	e3	e3	e3	e3
memory density	2147483648 bit	2147483648 bit	2147483648 bit	2147483648 bit
Memory IC Type	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE
memory width	64	64	64	64
Number of terminals	240	240	240	240
word count	33554432 words	33554432 words	33554432 words	33554432 words
character code	32000000	32000000	32000000	32000000
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C
organize	32MX64	32MX64	32MX64	32MX64
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DIMM	DIMM	DIMM	DIMM
Encapsulate equivalent code	DIMM240,40	DIMM240,40	DIMM240,40	DIMM240,40
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	1.8 V	1.8 V	1.8 V	1.8 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
refresh cycle	8192	8192	8192	8192
Maximum standby current	0.02 A	0.02 A	0.02 A	0.02 A
Maximum slew rate	1.12 mA	1.4 mA	1.4 mA	1.26 mA
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER	OTHER
Terminal form	NO LEAD	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	1 mm	1 mm	1 mm	1 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Base Number Matches	1	1	1	1

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