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EDI88130LPS20FC

Description
Standard SRAM, 128KX8, 20ns, CMOS, CDFP32, CERAMIC, DFP-32
Categorystorage    storage   
File Size500KB,9 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Download Datasheet Parametric View All

EDI88130LPS20FC Overview

Standard SRAM, 128KX8, 20ns, CMOS, CDFP32, CERAMIC, DFP-32

EDI88130LPS20FC Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Parts packaging codeDFP
package instructionDFP, FL32,.4
Contacts32
Reach Compliance Codecompliant
ECCN code3A991.B.2.B
Maximum access time20 ns
Other featuresBATTERY BACKUP OPERATION
I/O typeCOMMON
JESD-30 codeR-CDFP-F32
length20.828 mm
memory density1048576 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize128KX8
Output characteristics3-STATE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDFP
Encapsulate equivalent codeFL32,.4
Package shapeRECTANGULAR
Package formFLATPACK
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Maximum seat height2.9464 mm
Maximum standby current0.002 A
Minimum standby current2 V
Maximum slew rate0.225 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width10.414 mm
Base Number Matches1
White Electronic Designs
128Kx8 Monolithic SRAM, SMD 5962-89598
FEATURES
Access Times of 15*, 17, 20, 25, 35, 45, 55ns
Battery Back-up Operation
• 2V Data Retention (EDI88130LPS)
CS1#, CS2 & OE# Functions for Bus Control
Inputs and Outputs Directly TTL Compatible
Organized as 128Kx8
Commercial, Industrial and Military Temperature
Ranges
Thru-hole and Surface Mount Packages JEDEC
Pinout
• 32 pin Sidebrazed Ceramic DIP, 400 mil
(Package 102)
• 32 pin Sidebrazed Ceramic DIP, 600 mil
(Package 9)
• 32 lead Ceramic SOJ (Package 140)
• 32 pad Ceramic Quad LCC (Package 12)
• 32 pad Ceramic LCC (Package 141)
• 32 lead Ceramic Flatpack (Package 142)
EDI88130CS
Single +5V (±10%) Supply OperationThe
EDI88130CS is a high speed, high performance,
128Kx8 bits monolithic Static RAM.
An additional chip enable line provides system memory
security during power down in non-battery backed up
systems and memory banking in high speed battery
backed systems where large multiple pages of memory
are required.
The EDI88130CS has eight bi-directional input-output lines
to provide simultaneous access to all bits in a word.
A low power version, EDI88130LPS, offers a 2V data
retention function for battery back-up applications.
Military product is available compliant to MIL-PRF-
38535.
* 15ns access time is advanced information, contact factory for availability.
FIGURE 1 – PIN CONFIGURATION
32 DIP
32 SOJ
32 CLCC
32 FLATPACK
TOP VIEW
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CS2#
WE#
A13
A8
A9
A11
OE#
A10
CS1#
I/O7
I/O6
I/O5
I/O4
I/O3
32 QUAD LCC
TOP VIEW
A12
A14
A16
NC
V
CC
A15
CS2
PIN DESCRIPTION
I/O0-7
A0-16
WE#
CS1#, CS2
OE#
V
CC
V
SS
NC
Data Input/Output
Address Inputs
Write Enable
Chip Select
Output Enable
Power Supply
Ground
Not Connected
4
3
2
1
32
31
30
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
29
28
27
26
25
24
23
22
21
WE#
A13
A8
A9
A11
OE#
A10
CS1#
I/O7
Block Diagram
Memory Array
I/O1
I/O2
V
SS
I/O3
I/O4
I/O5
I/O6
A0-16
Address
Buffer
Address
Decoder
I/O
Circuits
I/O0-7
WE#
CS1#
CS2
OE#
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2002
Rev. 11
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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