MT8941B
Advanced T1/CEPT Digital Trunk PLL
Data Sheet
Features
•
•
Provides T1 clock at 1.544 MHz locked to an 8
kHz reference clock (frame pulse)
Provides CEPT clock at 2.048 MHz and ST-BUS
clock and timing signals locked to an internal or
external 8 kHz reference clock
Typical inherent output jitter (unfiltered)= 0.07 UI
peak-to-peak
Typical jitter attenuation at: 10 Hz=23 dB,100
Hz=43 dB, 5 to 40 kHz
≥
64 dB
Jitter-free “FREE-RUN” mode
Uncommitted two-input NAND gate
Low power CMOS technology
Ordering Information
MT8941BE
24 Pin PDIP
Tubes
MT8941BP
28 Pin PLCC
Tubes
MT8941BPR 28 Pin PLCC
Tape & Reel
MT8941BP1 28 Pin PLCC* Tubes
MT8941BPR1 28 Pin PLCC* Tape & Reel
*Pb Free Matte Tin
February 2005
•
•
•
•
•
-40°C to +85°C
Description
The MT8941B is a dual digital phase-locked loop
providing the timing and synchronization signals for the
T1 or CEPT transmission links and the ST-BUS. The
first PLL provides the T1 clock (1.544 MHz)
synchronized to the input frame pulse at 8 kHz. The
timing signals for the CEPT transmission link and the
ST-BUS are provided by the second PLL locked to an
internal or an external 8 kHz frame pulse signal.
The MT8941B offers improved jitter performance over
the MT8940. The two devices also have some
functional differences, which are listed in the section on
“Differences between MT8941B and MT8940”.
Applications
•
•
Synchronization and timing control for T1
and CEPT digital trunk transmission links
ST- BUS clock and frame pulse source
F0i
DPLL #1
C12i
2:1 MUX
Variable
Clock
Control
CVb
CV
ENCV
MS0
MS1
MS2
MS3
C8Kb
Mode
Selection
Logic
Frame Pulse
Control
Input
Selector
4.096 MHz
Clock
Control
DPLL #2
F0b
C4b
C4o
ENC4o
C2o
C2o
ENC2o
C16i
Clock
Generator
Ai
Bi
2.048 MHz
Clock
Control
Yo
V
DD
V
SS
RST
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT8941B
Data Sheet
24 PIN PDIP
Figure 2 - Pin Connections
Pin Description
Pin #
DIP
PLCC
Name
Description
1
1
EN
CV
Variable clock enable (TTL compatible input)
- This input directly controls the three states
of CV (pin 22) under all modes of operation. When HIGH, enables CV and when LOW, puts
it in high impedance condition. It also controls the three states of CVb signal (pin 21) if MS1
is LOW. When ENCV is HIGH, the pin CVb is an output and when LOW, it is in high
impedance state. However, if MS1 is HIGH, CVb is always an input.
MS0
C12i
MS1
F0i
F0b
Mode select ‘0’ input (TTL compatible) -
This input in conjunction with MS1 (pin 4) selects
the major mode of operation for both DPLLs. (Refer to Tables 1 and 2.)
12.352 MHz Clock input (TTL compatible) -
Master clock input for DPLL #1.
Mode select-1 input (TTL compatible) -
This input in conjunction with MS0 (pin 2) selects
the major mode of operation for both DPLLs. (Refer to Tables 1 and 2.)
Frame pulse input (TTL compatible) -
This is the frame pulse input at 8 kHz. DPLL #1
locks to the falling edge of this input to generate T1 (1.544 MHz) clock.
Frame pulse Bidirectional (TTL compatible input and Totem-pole output) -
Depending
on the minor mode selected for DPLL #2, it provides the 8 kHz frame pulse output or acts as
an input to an external frame pulse.
Mode select-2 input (TTL compatible) -
This input in conjunction with MS3 (pin 17) selects
the minor mode of operation for DPLL #2. (Refer to Table 3.)
16.384 MHz Clock input (TTL compatible) -
Master clock input for DPLL #2.
2
3
4
5
6
2
3
6
7
8
7
8
9
10
9
10
11
12
MS2
C16i
EN
C4o
Enable 4.096 MHz clock (TTL compatible input) -
This active high input enables C4o (pin
11) output. When LOW, the output C4o is in high impedance condition.
C8Kb
Clock 8 kHz Bidirectional (TTL compatible input and Totem-pole output) -
This is the 8
kHz input signal on the falling edge of which the DPLL #2 locks during its NORMAL mode.
When DPLL #2 is in SINGLE CLOCK mode, this pin outputs an 8 kHz internal signal
provided by DPLL #1 which is also connected internally to DPLL #2.
2
Zarlink Semiconductor Inc.
C8Kb
C4o
VSS
C4b
C2o
C2o
NC
ENVC
MS0
C12i
MS1
F0i
F0b
MS2
C16i
ENC4o
C8Kb
C4o
VSS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
RST
CV
CVb
Yo
Bi
Ai
MS3
ENC2o
C2o
C2o
C4b
4
3
2
1
28
27
26
NC
C12i
MS0
ENCV
VDD
RST
CV
12
13
14
15
16
17
18
NC
MS1
F0i
F0b
MS2
C16i
ENC4o
5
6
7
8
9
10
11
•
25
24
23
22
21
20
19
NC
CVb
Yo
Bi
Ai
MS3
ENC2o
28 PIN PLCC
MT8941B
Pin Description (continued)
Pin #
DIP
PLCC
Data Sheet
Name
C4o
Description
Clock 4.096 MHz (Three state output)
- This is the inverse of the signal appearing on pin
13 (C4b) at 4.096 MHz and has a rising edge in the frame pulse (F0b) window. The high
impedance state of this output is controlled by ENC4o (pin 9).
Ground (0 Volt)
Clock 4.096 MHz- Bidirectional (TTL compatible input and Totem-pole output)
- When
the mode select bit MS3 (pin 17) is HIGH, it provides the 4.096 MHz clock output with the
falling edge in the frame pulse (F0b) window. When pin 17 is LOW, C4b is an input to an
external clock at 4.096 MHz.
Clock 2.048 MHz (Three state output)
- This is the divide by two output of C4b (pin 13) and
has a falling edge in the frame pulse (F0b) window. The high impedance state of this output
is controlled by EN
C2o
(pin 16).
Clock 2.048 MHz (Three state output) -
This is the divide by two output of C4b (pin 13) and
has a rising edge in the frame pulse (F0b) window. The high impedance state of this output is
controlled by EN
C2o
(pin 16).
11
13
12
13
14
15
V
SS
C4b
14
16
C2o
15
17
C2o
16
19
EN
C2o
Enable 2.048 MHz clock (TTL compatible input) -
This active high input enables both C2o
and C2o outputs (pins 14 and 15). When LOW, these outputs are in high impedance
condition.
MS3
Ai, Bi
Y
o
CVb
Mode select 3 input (TTL compatible) -
This input in conjunction with MS2 (pin 7) selects
the minor mode of operation for DPLL #2. (Refer to Table 3.)
Inputs A and B (TTL compatible) -These
are the two inputs of the uncommitted NAND
gate
.
Output Y (Totem pole output) -
Output of the uncommitted NAND gate.
Variable clock Bidirectional (TTL compatible input and Totem-pole output) -
When
acting as an output (MS1-LOW) during the NORMAL mode of DPLL #1, this pin provides the
1.544 MHz clock locked to the input frame pulse F0i (pin 5). When MS1 is HIGH, it is an
input to an external clock at 1.544 MHz or 2.048 MHz to provide the internal signal at 8 kHz
to DPLL #2.
Variable clock (Three state output) -
This is the inverse output of the signal appearing on
pin 21, the high impedance state of which is controlled by EN
CV
(pin 1).
Reset (Schmitt trigger input)
- This input (active LOW) puts the MT8941B in its reset state.
To guarantee proper operation, the device must be reset after power-up. The time constant
for a power-up reset circuit (see Figures 9-13) must be a minimum of five times the rise time
of the power supply. In normal operation, the RST pin must be held low for a minimum of
60 nsec to reset the device.
V
DD
(+5 V)
Power supply.
No Connection.
17
18,
19
20
21
20
21,
22
23
24
22
23
26
27
CV
RST
24
28
4,
5,
18,
25
V
DD
NC
3
Zarlink Semiconductor Inc.
MT8941B
Functional Description
Data Sheet
The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals to the interface
circuits for T1 and CEPT (30+2) Primary Multiplex Digital Transmission links. As shown in the functional block
diagram (see Figure 1), the MT8941B has two digital phase-locked loops (DPLLs), associated output controls and
the mode selection logic circuits. The two DPLLs, although similar in principle, operate independently to provide T1
(1.544 MHz) and CEPT (2.048 MHz) transmission clocks and ST-BUS timing signals.
The principle of operation behind the two DPLLs is shown in Figure 3. A master clock is divided down to 8 kHz
where it is compared with the 8 kHz input, and depending on the output of the phase comparison, the master clock
frequency is corrected.
Master clock
(12.352 MHz /
16.384 MHz)
Frequency
Correction
÷
8
Output
(1.544 MHz /
2.048 MHz)
Input
(8 kHz)
Phase
Comparison
÷
193 /
÷
256
Figure 3 - DPLL Principle
The MT8941B achieves the frequency correction in both directions by using three methods; speed-up, slow-down
and no-correction.
As shown in Figure 4, the falling edge of the 8 kHz input signal (C8Kb for DPLL #2 or F0i for DPLL # 1) is used to
sample the internally generated 8 kHz clock and the correction signal (CS) once in every frame (125
µs).
If the
sampled CS is “1”, then the DPLL makes a speed-up or slow-down correction depending upon the sampled value
of the internal 8 kHz signal. A sampled ”0” or “1” causes the frequency correction circuit to respectively stretch or
shrink the master clock by half a period at one instant in the frame. If the sampled CS is “0”, then the DPLL makes
no correction on the master clock input. Note that since the internal 8 kHz signal and the CS signal are derived from
the master clock, a correction will cause both clocks to stretch or shrink simultaneously by an amount equal to half
the period of the master clock.
Once in synchronization, the falling edge of the reference signal (C8Kb or F0i) will be aligned with either the falling
or the rising edge of CS. It is aligned with the rising edge of CS when the reference signal is slower than the internal
8 kHz signal. On the other hand, the falling edge of the reference signal will be aligned with the falling edge of CS
if the reference signal is faster than the internal 8 kHz signal.
C8Kb (DPLL #2)
or F0i (DPLL #1)
Interna
l
8 kHz
correction
CS
F0b
(DPLL #2)
speed-up
region
correction
slow-down
region
sampling edge
t
CS
no-correction
t
CSF
DPLL #1
:
DPLL #2:
t
CS
= 4
×
T
P12
±
0.5
×
T
P12
t
CS
= 512
×
T
P16
±
0.5
×
T
P16
t
CSF
= 766
×
T
P16
where, T
P12
is the 12.352 MHz master clock oscillator period
for DPLL #1 and T
P16
is the 16.384 MHz master clock period
for DPLL #2.
Figure 4 - Phase Comparison
4
Zarlink Semiconductor Inc.
MT8941B
Input-to-Output Phase Relationship
Data Sheet
The no-correction window size is 324 ns for DPLL #1 and 32
µs
for DPLL #2. It is possible for the relative phase of
the reference signal to swing inside the no-correction window depending on its jitter and the relative drift of the
master clock. As a result, the phase relationship between the input signal and the output clocks (and frame pulse in
case of DPLL #2) may vary up to a maximum of window size. This situation is illustrated in Figure 4. The maximum
phase variation for DPLL #1 is 324 ns and for DPLL #2 it is 32
µs.
However, this phase difference can be absorbed
by the input jitter buffer of Zarlink’s T1/CEPT devices.
The no-correction window acts as a filter for low frequency jitter and wander since the DPLL does not track the
reference signal inside it. The size of the no-correction window is less than or equal to the size of the input jitter
buffer on the T1 and CEPT devices to guarantee that no slip will occur in the received T1/CEPT frame.
The circuit will remain in synchronization as long as the input frequency is within the lock-in range of the DPLLs
(refer to the section on “Jitter Performance and Lock-in Range” for further details). The lock-in range is wide enough
to meet the CCITT line rate specification (1.544 MHz
±32
ppm and 2.048 MHz
±50
ppm) for the High Capacity
Terrestrial Digital Service.
The phase sampling is done once in a frame (8 kHz) for each DPLL. The divisions are set at 8 and 193 for DPLL #1,
which locks to the falling edge of the input at 8 kHz to generate T1 (1.544 MHz) clock. For DPLL #2, the divisions
are set at 8 and 256 to provide the CEPT/ST-BUS clock at 2.048 MHz synchronized to the falling edge of the input
signal (8 kHz). The master clock source is specified to be 12.352 MHz for DPLL #1 and 16.384 MHz for DPLL #2
over the entire temperature range of operation.
The inputs MS0 to MS3 are used to select the operating mode of the MT8941B, see Tables 1 to 4. All the outputs
are controlled to the high impedance condition by their respective enable controls. The uncommitted NAND gate is
available for use in applications involving Zarlink’s MT8976/ MH89760 (T1 Interfaces) and MT8979/MH89790
(CEPT Interfaces).
Modes of Operation
The operation of the MT8941B is categorized into major modes and minor modes. The major modes are defined for
both DPLLs by the mode select pins MS0 and MS1. The minor modes are selected by pins MS2 and MS3 and are
applicable only to DPLL #2. There are no minor modes for DPLL #1.
Major modes of DPLL #1
DPLL #1 can be operated in three major modes as selected by MS0 and MS1 (Table 1). When MS1 is LOW, it is in
NORMAL mode, which provides a T1 (1.544 MHz) clock signal locked to the falling edge of the input frame pulse
F0i (8 kHz). DPLL #1 requires a master clock input of 12.352 MHz (C12i). In the second and third major modes
(MS1 is HIGH), DPLL #1 is set to DIVIDE an external 1.544 MHz or 2.048 MHz signal applied at CVb (pin 21). The
division can be set by MS0 to be either 193 (LOW) or 256 (HIGH). In these modes, the 8 kHz output at C8Kb is
connected internally to DPLL #2, which operates in SINGLE CLOCK mode.
Major modes of DPLL #2
There are four major modes for DPLL #2 selectable by MS0 and MS1, as shown in Table 2. In all these modes
DPLL #2 provides the CEPT PCM30 timing, and the ST-BUS clock and framing signals.
In NORMAL mode, DPLL #2 provides the CEPT/ST-BUS compatible timing signals locked to the falling edge of the
8 kHz input signal (C8Kb). These signals are 4.096 MHz (C4o and C4b) and 2.048 MHz (C2o and C2o) clocks, and
the 8 kHz frame pulse (F0b) derived from the 16.384 MHz master clock. This mode can be the same as the FREE-
RUN mode if the C8Kb pin is tied to V
DD
or V
SS
.
5
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