5841
AND
5842
UCN5841A & UCN5842A
V
EE
CLOCK
SERIAL
DATA IN
LOGIC
GROUND
LOGIC
SUPPLY
SERIAL
DATA OUT
STROBE
OUTPUT
ENABLE
V
EE
1
2
3
4
5
6
7
8
9
ST
OE
V
DD
18
SUB
CLK
SHIFT REGISTER
17
16
LATCHES
15
14
13
12
11
10
SUB
Dwg. PP-026-1
BiMOS II 8-BIT SERIAL-INPUT,
LATCHED DRIVERS
The merging of low-power CMOS logic and bipolar output power
drivers permit the UCN5841/42A, UCN5841/42LW, and A5841/42SLW
integrated circuits to be used in a wide variety of peripheral power
driver applications. Each device has an eight-bit CMOS shift register
and CMOS control circuitry, eight CMOS data latches, and eight bipolar
current-sinking Darlington output drivers. The 500 mA npn Darlington
outputs, with integral transient-suppression diodes, are suitable for use
with relays, solenoids, and other inductive loads. Except for packaging
and the maximum driver output voltage ratings, the UCN5841A,
UCN5841LW, A5841SLW, UCN5842A, UCN5842LW, and A5842SLW
are identical. All package variations of the 5842 offer premium perfor-
mance with a minimum output-breakdown voltage rating of 80 V (50 V
sustaining). All drivers can be operated with a split supply where the
negative supply is up to -20 V.
BiMOS II devices have higher data-input rates than the earlier
BiMOS circuits. With a 5 V logic supply, they will typically operate at
better than 5 MHz. With a 12 V supply, significantly higher speeds are
obtained. The CMOS inputs are compatible with standard CMOS and
NMOS logic levels. TTL circuits may require the use of appropriate
pull-up resistors. By using the serial data output, drivers can be
cascaded for interface applications requiring additional drive lines.
The UCN584xA devices are furnished in a standard 18-pin plastic
DIP; the UCN584xLW devices are in an 18-lead surface-mountable
wide-body SOIC package; the A584xSLW devices are provided in a 20-
lead wide-body SOIC package with improved thermal characteristics.
The A5841SLW and UCN5841LW drivers are also available for
operation to a temperature of -40°C. To order, change the suffix from
‘SLW’ to ‘ELW’, or change the prefix from ‘UCN’ to ‘UCQ’.
Data Sheet
26185.14F
OUT
1
OUT
2
OUT
3
OUT
4
OUT
5
OUT
6
OUT
7
OUT
8
K
Note that the UCN584xA (dual in-line package) and
UCN584xLW (small-outline IC package) are electrically
identical and share a common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at 25
°
C Free-Air Temperature
Output Voltage, V
CE
(5841) . . . . . . . . . . . . . . . . . . . . . .
50 V
(5842) . . . . . . . . . . . . . . . . . . . . . .
80 V
Output Voltage, V
CE(sus)
(5841) . . . . . . . . . . . . . . . . . . . . .
35 V†
(5842) . . . . . . . . . . . . . . . . . . . . .
50 V†
Logic Supply Voltage Range,
V
DD
. . . . . . . . . . . . . . . .
4.5 V to 15 V
V
DD
with Reference to V
EE
. . . . .
25 V
Emitter Supply Voltage, V
EE
. . . . . . .
-20 V
Input Voltage Range,
V
IN
. . . . . . . . . . .
-0.3 V to V
DD
+ 0.3 V
Continuous Output Current,
I
OUT
. . . . . . . . . . . . . . . . . . . .
500 mA
Package Power Dissipation,
P
D
. . . . . . . . . . . . . . . . . . .
See Graph
Operating Temperature Range,
T
A
. . . . . . . . . . . . . . . .
-20
°
C to +85
°
C
Storage Temperature Range,
T
S
. . . . . . . . . . . . . . .
-55
°
C to +150
°
C
†For inductive load applications.
Caution: CMOS devices have input static protection
but are susceptible to damage when exposed to
extremely high static electrical charges.
FEATURES
I
To 3.3 MHz Data-Input Rate
I
CMOS, NMOS, TTL Compatible Inputs
I
Internal Pull-Up/Pull-Down Resistors
I
Low-Power CMOS Logic and Latches,
I
High-Voltage Current-Sink Outputs
I
Output Transient-Protection Diodes
I
Single or Split Supply Operation
I
DIP or SOIC Packaging
I
Automotive Capable
Always order by complete part number, e.g.,
A5841SLW
.
5841
AND
5842
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
TYPICAL INPUT CIRCUITS
V
DD
CLOCK
A
B
DATA IN
E
C
STROBE
F
D
STROBE
IN
OUTPUT
ENABLE
OUTPUT
ENABLE
OUT
N
G
Dwg. No. A-12,627
Dwg. EP-010-3
VDD
TIMING CONDITIONS
(T
A
= +25
°
C, V
DD
= 5.0 V, Logic Levels are V
DD
and Ground)
A.
Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75 ns
CLOCK
SERIAL
DATA IN
B.
Minimum Data Active Time After Clock Pulse
(Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75 ns
C.
Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
150 ns
D.
Minimum Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
150 ns
E.
Minimum Time Between Clock Activation and Strobe . . . . . . . . . . . .
300 ns
F.
Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100 ns
Dwg. EP-010-4A
G.
Typical Time Between Strobe Activation and
Output Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.0
µ
s
TYPICAL OUTPUT DRIVER
K
Serial Data present at the input is transferred to the shift register
on the logic “0” to logic “1” transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to its respective
latch when the STROBE is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as the STROBE is held
high. Applications where the latches are bypassed (STROBE tied high)
will require that the ENABLE input be high during serial data entry.
When the ENABLE input is high, all of the output buffers are
disabled (OFF) without affecting the information stored in the latches or
shift register. With the ENABLE input low, the outputs are controlled by
the state of the latches.
OUT
V
EE
SUB
Dwg. EP-021-8
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5841
AND
5842
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I
1
I
2
I
3
.............. I
8
H
L
X
H
L
R
1
R
2
.............. R
7
R
1
R
2
.............. R
7
Serial
Data Strobe
Output Input
R
7
R
7
R
8
X
P
8
L
H
R
1
R
2
R
3
.............. R
8
P
1
P
2
P
3
.............. P
8
X
L = Low Logic Level
H = High Logic Level
X = Irrelevant
X
X
.............. X
L
H
P
1
P
2
P
3
..............
P
8
Latch Contents
I
1
I
2
I
3
.............. I
8
Output
Enable
Output Contents
I
1
I
2
I
3
..............
I
8
R
1
R
2
R
3
.............. R
8
X
X
X
.............. X
P
1
P
2
P
3
.............. P
8
H H H .............. H
P = Present State
R = Previous State
TYPICAL APPLICATION
RELAY/SOLENOID DRIVER
Using Split Supply
UCN5842A
The products described here are manufactured
under one or more U.S. patents or U.S. patents
pending.
Allegro MicroSystems, Inc. reserves the right to
make, from time to time, such departures from the detail
specifications as may be required to permit improve-
ments in the performance, reliability, or
manufacturability of its products. Before placing an
order, the user is cautioned to verify that the informa-
tion being relied upon is current.
Allegro products are not authorized for use as
critical components in life-support devices or systems
without express written approval.
The information included herein is believed to be
accurate and reliable. However, Allegro
MicroSystems, Inc. assumes no responsibility for its
use; nor for any infringement of patents or other rights
of third parties which may result from its use.
Dwg. No. A-12,547
www.allegromicro.com
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