Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.
NOT AN OFFER FOR SALE
The information
presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale
or an offer for sale that creates a contractual power of acceptance. "QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semicondor, IDT, and Micron Tecnology, Inc."
DSC-5677/1
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-II
TM
Preliminary Datasheet
Commercial Temperatue Range
Pin Configuration
70P3537
70P3517
RM-576 Ball Flip Chip BGA
Top View
A1 BALL PAD CORNER
1
A
V
SS
2
V
SS
D17
R
3
ZQ
R
V
SS
4
V
SS
5
6
7
8
A3
R
A4
R
A1
R
V
SS
V
DDQR
V
SS
V
DDQR
9
10
BW
11
E0
R
E1
R
K
R
V
DDQR
V
SS
V
DD
V
SS
12
V
DD
V
SS
K
R
V
SS
V
DD
V
SS
V
DD
13
V
REFR
V
DD
C
R
V
SS
V
DD
V
SS
V
DD
14
BW
15
A8
R
W
16
A9
R
A12
R
A11
R
V
DDQR
V
SS
V
DD
V
SS
17
A14
R
A13
R
A16
R
V
SS
V
DDQR
V
SS
V
DDQR
18
A15
R
INC
A17
R
V
DDQR
V
SS
V
DDQR
V
SS
19
V
DDQR
V
SS
20
V
SS
V
SS
21
22
23
V
SS
24
A
V
SS
V
SS
V
DDQR
A2
R
V
SS
EP
0
R
R
A5
R
A6
R
V
DDQR
V
SS
V
DD
V
SS
0R
3R
M R ST D
OFFR
V
SS
Q35
R
Q33
R
Q31
R
Q29
R
Q27
R
B
V
SS
V
DDQR
D
EPTH
BW
1R
B
BW
2R
R
V
DDQR
D35
R
V
SS
D33
R
V
SS
C
D16
R
D15
R
V
DDQR
Q17
R
D13
R
V
SS
Q15
R
V
SS
V
DDQR
Q16
R
A0
R
A7
R
V
SS
V
DD
V
SS
V
DD
C
R
V
DDQR
V
SS
V
DD
V
SS
A10
R
V
SS
V
DD
V
SS
V
DD
V
DDQR
V
DDQR
V
SS
V
DDQR
V
SS
V
DDQR
Q34
R
Q32
R
Q30
R
Q28
R
D34
R
C
D
D14
R
V
SS
V
DDQR
V
DDQR
D31
R
V
SS
D29
R
D32
R
D
E
D12
R
D11
R
V
DDQR
Q13
R
D10
R
V
SS
V
SS
V
DDQR
Q11
R
Q9
R
Q14
R
V
DDQR
V
SS
Q12
R
V
SS
V
DDQR
D30
R
E
F
V
SS
V
DDQR
D27
R
V
SS
D26
R
D28
R
F
G
V
REFR
Q10
R
V
DDQR
V
SS
V
SS
G
H
D9
R
D8
R
V
SS
Q8
R
Q6
R
Q4
R
Q2
R
Q0
R
Q17
L
Q15
L
Q13
L
CQ
R
V
SS
V
DDQR
V
SS
V
SS
V
DDQR
V
SS
V
DDQR
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
SS
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
SS
V
DDQR
V
SS
V
DDQR
V
SS
V
DDQL
V
SS
V
DDQL
V
DDQR
V
SS
V
DDQR
V
SS
V
DDQR
V
SS
V
DDQL
V
SS
V
SS
V
DDQR
V
SS
V
DDQR
V
SS
V
DDQL
V
SS
V
DDQL
CQ
R
Q25
R
Q23
R
Q21
R
Q19
R
Q34
L
Q32
L
Q30
L
Q26
R
Q24
R
Q22
R
Q20
R
Q18
R
Q35
L
Q33
L
Q31
L
V
DDQR
V
SS
V
SS
D24
R
V
REFR
H
J
D7
R
D6
R
V
DDQR
D4
R
V
SS
Q7
R
V
DDQR
Q5
R
D25
R
J
K
D5
R
V
SS
V
DDQR
V
SS
V
DDQR
D22
R
V
SS
D20
R
D23
R
K
L
D3
R
D2
R
V
DDQR
D0
R
Q3
R
V
DDQR
Q1
R
D21
R
L
M
D1
R
V
SS
V
SS
V
DDQR
V
SS
V
DDQL
V
SS
V
DDQL
V
SS
V
DDQL
V
SS
V
DD
V
SS
V
DD
V
DDQR
D18
R
V
SS
D35
L
D19
R
M
N
D16
L
D17
L
V
DDQL
D15
L
V
SS
Q16
L
V
DDQL
Q14
L
V
SS
D34
L
N
P
D14
L
V
DDQL
D33
L
V
SS
D31
L
D32
L
P
R
D12
L
D13
L
V
DDQL
Q12
L
V
DDQL
V
SS
V
DDQL
V
SS
V
DDQL
D30
L
R
T
D10
L
D11
L
V
SS
D9
L
D8
L
D6
L
D4
L
D2
L
D0
L
V
SS
V
SS
V
DDQL
V
SS
V
DDQL
V
SS
V
DDQL
V
SS
V
DDQL
ZQ
L
Q11
L
Q9
L
Q8
L
Q6
L
Q4
L
Q2
L
Q0
L
V
SS
V
SS
Q10
L
V
SS
V
SS
V
DDQL
V
SS
V
DDQL
V
SS
V
DDQL
A1
L
A4
L
A3
L
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
SS
K
L
V
DD
V
REFL
V
SS
V
DD
V
SS
V
DD
V
SS
V
SS
C
L
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DDQL
V
SS
V
DDQL
V
SS
V
DDQL
V
SS
V
DDQL
V
SS
Q28
L
Q29
L
Q27
L
Q26
L
Q24
L
Q22
L
Q20
L
Q18
L
V
DDQL
TCK
V
DDQL
D29
L
V
SS
V
DDQL
D27
L
V
SS
D25
L
D28
L
T
U
V
REFL
CQ
L
V
DDQL
Q7
L
Q5
L
Q3
L
V
SS
CQ
L
Q25
L
Q23
L
Q21
L
Q19
L
V
DDQL
V
SS
TR ST
D26
L
U
V
V
SS
V
REFL
V
W
D7
L
V
DDQL
V
SS
V
SS
V
DDQL
V
SS
A0
L
V
SS
V
DD
V
SS
A6
L
A5
L
R
L
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
A11
L
A12
L
A9
L
V
DDQL
V
SS
V
DDQL
A16
L
A13
L
A14
L
V
SS
V
DDQL
V
SS
A17
L
INC
A15
L
V
DDQL
V
SS
V
DDQL
V
SS
V
DDQL
V
SS
V
SS
V
SS
W
Y
D5
L
V
DDQL
D24
L
V
SS
D22
L
D23
L
Y
AA
D3
L
Q1
L
V
DDQL
V
DDQL
V
SS
TDI
TMS
V
DDQL
V
DDQL
A7
L
K
L
E1
L
E0
L
V
DDQL
V
DDQL
C
L
A10
L
D21
L
AA
AB
D1
L
V
DDQL
D20
L
D
OFFL
D18
L
TDO
V
SS
D19
L
AB
AC
V
SS
V
DDQL
EP1
V
SS
A2
L
BW
1L
AC
V
SS
V
DD
BW
2L
W
L
V
SS
AD
V
SS
BW
0L
AD
BW
3L
A8
L
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
5677 drw
NOTE:
1. The package is 25mm x 25mm x 2.55mm with 1.0mm ball pitch; the customer will have to provide external airflow of 100LFM (0.5m/s) or higher at 250MHz.
2
January 29, 2009
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-II
TM
Preliminary Datasheet
Commercial Temperatue Range
Functional Description
As a memory standard, the (Quad Data Rate) QDR-II SRAM
interface has become increasingly common in high performance
networking systems. With the QDR-II interface/configuration, memory
throughput is increased without increasing the clock rate via the use
of two unidirectional buses on each of providing 2 ports of QDR-II
makes this a Dual-QDRII Static Ram two ports to transfer data without
the need for bus turnaround.
Dual QDR-II Static RAMs are high speed synchronous mem-
ories supporting two independent double-data-rate (DDR) read and
write data ports. This scheme allows simultaneous read and write
access for the maximum device throughput - two data items are
passed with each read or write. Four data word transfers occur per
clock cycle, providing quad-data-rate (QDR) performance on each
port. Comparing this with standard SRAM common I/O single data
rate (SDR) devices, a four to one increase in data access is achieved
at equivalent clock speeds. IDT70P3537/70P3517 Dual QDR-II Static
RAM devices, are capable of sustaining full bandwidth on both the
input and output buses simultaneously. Using independent buses for
read and write data access simplifies design by eliminating the need
for bidirectional buses. And all data are in two word bursts, (with
addressing capability to the burst level).
Devices with QDR-II interfaces include network processor units
(NPUs) and field programmable gate arrays (FPGAs).
IDT70P3537/70P3517 Dual QDR-II Static RAMs support uni-
directional 36-bit read and write interfaces. These data inputs and
outputs operate simultaneously, thus eliminating the need for high-
speed bus turnarounds (i.e. no dead cycles are present). Access to
each port is accomplished using a common 18-bit address bus (17
bits for IDT70P3517). Addresses for reads and writes are latched on
rising edges of the K and
K
input clocks, respectively.The K and
K
clocks are offset by 90 degrees or half a clock cycle. Each address
location is associated with two 36-bit data words that burst sequentially
into or out of the device. Since data can be transferred into and out
of the device on every rising edge of the K and
K
clocks, memory
bandwidth is maximized while simplifying overall design through the
elimination of bus turnaround(s). IDT70P3537/70P3517 Dual QDR-II
Static RAMs can support devices in a multi-drop configuration (i.e.
multiple devices connected to the same interface). Through this
capability, system designers can support compatible devices such as
NPUs and FPGAs on the same bus at the same time.
Using independent ports for read and write access simplifies
design by eliminating the need for bidirectional buses. All buses
associated with Dual QDR-II Static RAMs are unidirectional and can
be optimized for signal integrity at very high bus speeds. The Dual
QDR-II Static RAM has scalable output impedance on its data output
bus and echo clocks allowing the user to tune the bus for low noise
and high performance.
IDT70P3537/70P3517 Dual QDR-II Static RAMs have a single
DDR address bus per port with multiplexed read and write addresses.
All read addresses are received on the first half of the clock cycle and
all write addresses are received on the second half of the clock cycle.
The byte write signals are received on both halves of the clock cycle
simultaneously with the data they are controlling on the data input bus.
The Dual QDR-II Static RAM device has echo clocks, which
provide the user with a clock that is precisely timed to the data output
3
and tuned with matching impedance and signal quality. The user
can use the echo clock for downstream clocking of the data. For
the user, echo clocks eliminate the need to produce alternate clocks
with precise timing, positioning, and signal qualities to guarantee
data capture. Since the echo clocks are generated by the same
source that drives the data output, the relationship to the data is
NOT significantly affected by external parameters such as voltage,
temperature, and process as would be the case if the clock were
generated by an outside source.Thus the echo clocks are guaran-
teed to be synchronized with the data.
All interfaces of Dual QDR-II Static RAMs are HSTL, allow-
ing speeds beyond SRAM devices that use any form of TTL
interface. The interface can be scaled to higher voltages (up to
1.9V) to interface with 1.8V systems, if necessary. The device has
VDDQ pins and a separate Vref, allowing the user to designate the
interface operational voltage independent of the device core volt-
age of 1.8V VDD. Output impedance control pins allow the user to
adjust the drive strength to adapt to a wide range of loads and
transmission lines.
Clocking
The IDT70P3537/3517 has two sets of input clocks for both
the input and output, the K,
K
clocks and the C,
C
clocks. In addition,
the IDT70P3537/3517 has an output “echo” clock pair, CQ and
CQ.
The K and
K
clocks are the primary device input clocks.
The K clock is used to clock in the control signals (R,
W,
E[1:0],
BW0-3),
the read address, and the first word of the data burst
(D[35:0]) during a write operation. The
K
clock is used to clock in
the control signals (BW
0-3
, E[1:0]), write address and the second
word of the data burst during a write operation (D[35:0]). In the
event that the user disables the C and
C
clocks, the K and
K
clocks
will also be used to clock the data out of the output register and
generate the echo clocks. The K and
K,
C and
C,CQ
and
CQ,
pairs
are offset by half a clock cycle from each other.
The C and
C
clocks may be used to clock the data out of
the output register during read operations and to generate the echo
clocks. C and
C
must be presented to the memory within the timing
tolerances as shown in the AC Electrical Characteristics Table
(Page 12). The output data from the IDT70P3537/70P3517 will be
closely aligned to the C and
C
input, through the use of an internal
DLL. When
C
is presented to the IDT70P3537/70P3517 the DLL
will have already internally clocked the data to arrive at the device
output simultaneously with the arrival of the
C
clock. The C and
second data item of the burst will also correspond.
Single Clock Mode
The IDT70P3537/70P3517 may be operated with a single
clock pair. C and
C
may be disabled by tying both signals high,
forcing the outputs and echo clocks to be controlled instead by the
K and
K
clocks.
DLL Operation
The DLL in the output structure of the IDT70P3537/70P3517
can be used to closely align the incoming clocks C and
C
with the
output of the data, generating very tight tolerances between the
January 29, 2009
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-II
TM
Preliminary Datasheet
Commercial Temperatue Range
two. The user may disable the DLL by holding
D
OFF
low. With the DLL
off, the C and
C
(or K and
K,
if C and
C
are not used) will directly clock
the output register of the IDT70P3537/70P3517. With the DLL off,
there will be a propagation delay from the time the clock enters the
device until the data appears at the output. QDR-II becomes QDRI
TM
with DLL off. First data out is referenced to C instead of
C.
Echo Clock
The echo clocks, CQ and
CQ,
are generated by the C and
C
clocks (or K,
K
if C,
C
are disabled). The rising edge of C generates
the rising edge of CQ, and the falling edge of
CQ.
The rising edge of
C
generates the rising edge of
CQ
and the falling edge of CQ. This
scheme improves the correlation of the rising and falling edges of the
echo clock and will improve the duty cycle of the individual signals.
The echo clock is very closely aligned with the data, guaranteeing
that the echo clock will remain closely correlated with the data, within
the tolerances designated.
Normal QDR-II Read and Write Operations
The IDT70P3537/70P3517 Dual QDR-II Static RAM supports
QDR-II burst-of-two read/write operations. Read operations are initi-
ated by holding the read port select (R) low, and presenting the read
address to the address port during the rising edge of K which will latch
the address. Data is delivered after the next rising edge of the next
K
(t + 1), using C and
C
as the output timing references; or K and
K,
if
C and
C
are tied high.
The write operation is a standard QDR-II burst-of-two write
operation, except the data is not available to be read until the next
clock cycle (this is one cycle later than standard QDR-II SRAM).
Normal QDR write cycles are initiated by holding the write port select
(W) low at K rising edge. Also, the Byte Write inputs (BW
0-3
), desig-
nating which bytes are to be written, need to be held low for both the
K and
K
clocks. On the rising edge of K the first word of the data must
also be present on the data input bus D[35:0] observing the designated
set up times. Upon the rising edge of K the first word of the burst will
be latched into the input register. After K has risen, and the designated
hold times observed, the second half of the clock cycle is initiated by
presenting the write address to the address bus A[X:0], the
BW0-3
inputs for the second data word of the burst, and the second data item
of the burst to the data bus D[35:0]. Upon the rising edge of
K,
the
second word of the burst will be latched, along with the designated
address. Both the first and second words of the burst will be written
into memory as designated by the address and byte write enables.
The addresses for the write cycles is provided at the
K
rising edge,
and data is expected at the rising edge of K and
K,
beginning at the
same K that initiated the cycle.
Programmable Impedance
An external resistor, RQ, must be connected between the
ZQ pin on the IDT70P3537/70P3517 and tied to V
SS
to allow the
IDT70P3537/70P3517 to adjust its output drive impedance. The value
of RQ must be 5X the value of the intended drive impedance of the
IDT70P3537/70P3517. The allowable range of RQ to guarantee
impedance matching with a tolerance of +/- 15% is 175 ohms to 350
ohms. The output impedance is adjusted every 1024 clock cycles to
correct for drifts in supply voltage and temperature. If the user wishes
to drive the output impedance of the IDT70P3537/70P3517 to its
lowest value, the ZQ pin may be tied to V
DDQ
.
4
January 29, 2009
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-II
TM
Preliminary Datasheet
Commercial Temperatue Range
Pin Definitions
Symbol
(1)
D[35:0]
X
Pin Function
Input
Synchronous
Input
Synchronous
Input
Synchronous
Output
Synchronous
Input
Synchronous
Input
Synchronous
Input Clock
Input Clock
Input Clock
Input Clock
Output Clock
Description
Data input signals, sampled on the rising edge of K and
K
clocks during valid write operations
Byte Write Selects active LOW. Sampled on the rising edge of the K and again on the rising edge of
K
clocks during write operations. Used to select which byte is
written into the device during the current portion of the write operations. Bytes not written remain unaltered. All byte writes are sampled on the same edge as the
data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written in to the device.
BW
0
controls D[8:0],
BW
1
controls D[17:9],
BW
2
controls D[26:18], and
BW
3
controls D[35:27].
Address Inputs. Read addresses are sampled on the rising edge of K clock during active read operations. Write addresses are sampled on the rising edge of
K
clock during active write operations. These address inputs are multiplxed, so that both a read and write operation can occur on the same clock cycle. These inputs
are ignored when the appropriate port is deselected.
Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and
C
clocks during
Read operations or K and
K
when operating in single clock mode. When the Read port is deselected, Q[35:0] are automatically tri-stated.
Write Control Logic, active LOW. Sampled on the rising edge of the positive input clock (K). When asserted active, a write operation in initiated. Deasserting will
deselect the Write port. Deselecting the Write port will cause D[35:0] to be ignored.
Read Control Logic, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a Read operation is initiated. Deasserting will cause the
Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next
rising edge of the
C
clock. (D
OFFX
= 1). Each read access consists of a burst of two sequential transfers.
Positive Output Clock Input. C is used in conjunction with
C
to clock out the Read data from the device. C and
C
can be used together to deskew the flight times of
various devices on the board back to the controller. See application example for further details.
Negative Output Clock Input.
C
is used in conjunction with C to clock out the Read data from the device. C and
C
can be used together to deskew the flight times
of various devices on the board back to the controller. See application example for further details.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device. Drives out data through Q[35:0] when in single clock mode.
All accesses are initiated on the rising edge of K.
Negative Input Clock Input.
K
is used to capture synchronous inputs being presented to the device. Drives out data through Q[35:0] when in single clock mode.
Synchronous Echo clock output. The rising edge of CQ is tightly matched to the synchronous data outputs and can be used as a data valid indication. CQ is free
running and does not stop when the output data is tri-stated.
Synchronous Echo Clock output. The rising edge of
CQ
is tightly matched to the synchronous data outputs and can be used as a data valid indication.
CQ
is free
running and does not stop wehen the output data is tri-stated.
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q[35:0] output impedance is set to 0.2 x RQ,
where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to V
DDQ
, which enables the minimum impedance mode.
This pin cannot be connected directly to GND or left unconnected.
EP[1:0] are used to program the Port Enable pins E[1:0]. EP[1:0] are programmed by tying the pins high or low on the board. If a customer does not want to use
Pins EP[1:0], then these pins should be tied low. Refer to Truth Table III for Port Enable pins.
Two Port Enable pins E[1:0] are provided to connect to the two MSB bits on the memory controller in order to cascade up to four IDT70P3537 devices. If a customer
does not want to use Pins E[1:0], then these pins should be tied low. Refer to Truth Table III for Port Enable pins. Also refer to Figure 1 showing cascade/multi-drop
using port-enable (E[1:0]) pins. E[1:0] are sampled on the rising edge of K for read operations and again on rising edge of
K
for write operations.
DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the DLL turned off will be different from those listed in this data sheet.
There will be an increased propagation delay from the incidence of C and
C
to Q, or K and
K
to Q as configured.
BW
0
X
,
BW
1
X
,
BW
2
X
,
BW
3
X
A[17:0]
X(2)
Q[35:0]
X
W
X
R
X
C
X
C
X
K
X
K
X
CQ
X
CQ
X
ZQ
X
Output Clock
Input
EP[1:0]
E
X
[1:0]
Input
Input
Syncronous
D
OFFX
MRST
DEPTH
TDO
TCK
TDI
TMS
TRST
INC
V
REF
X
V
DD
V
SS
V
DDQX
Input
Input
Master Reset pin. When held low will reset the device.
Asynchronous
Input
Output
Input
Input
Input
Connect to V
DDQ
for 9Mb. Connect to V
SS
for 18Mb.
TDO pin for JTAG.
TCK pin for JTAG.
TDI pin for JTAG.
TMS pin for JTAG.
Input
Reset pin for JTAG.
Asynchronous
Should be tied to V
CC
or V
SS
only, or can be left as a floating pin.
Input
Reference
Reference Voltage input. Static input used to set the reference level for HSTL inputs as well as AC measurement points.
Power Supply Power supply inputs to the core of the device. Should be connected to a 1.8V power supply.
Ground
Ground for the device. Should be connected to ground of the system.
Power Supply Power supply for the outputs of the device. Should be connected to a 1.5V power supply for HSTL or scaled to the desired output voltage.
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