notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
11/06/08
1
IS42VS32200E
GENERAL DESCRIPTION
The 64Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 1.8V
memory systems containing 67,108,864 bits. Internally
configured as a quad-bank DRAM with a synchronous
interface. Each 16,777,216-bit bank is organized as 2,048
rows by 256 columns by 32 bits.
The 64Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK.
All inputs and outputs are LVTTL compatible.
The 64Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE function
enabled. Precharge one bank while accessing one of the
other three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting
at a selected location and continuing for a programmed
number of locations in a programmed sequence. The
registration of an ACTIVE command begins accesses,
followed by a READ or WRITE command. The ACTIVE
command in conjunction with address bits registered are
used to select the bank and row to be accessed (BA0,
BA1 select the bank; A0-A10 select the row). The READ
or WRITE commands in conjunction with address bits
registered are used to select the starting column location
for the burst access.
Programmable READ or WRITE burst lengths consist of
1, 2, 4 and 8 locations or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
CS
RAS
CAS
WE
DQM0-3
COMMAND
DECODER
&
CLOCK
GENERATOR
DATA IN
BUFFER
32
32
MODE
REGISTER
11
REFRESH
CONTROLLER
DQ 0-31
SELF
REFRESH
CONTROLLER
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
11
32
DATA OUT
BUFFER
V
DD
/V
DDQ
GND/GNDQ
32
REFRESH
COUNTER
2048
2048
2048
2048
ROW DECODER
MULTIPLEXER
11
MEMORY CELL
ARRAY
ROW
ADDRESS
LATCH
11
ROW
ADDRESS
BUFFER
BANK 0
SENSE AMP I/O GATE
COLUMN
ADDRESS LATCH
256
(x 32)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN
ADDRESS BUFFER
COLUMN DECODER
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
11/06/08
IS42VS32200E
PIN CONFIGURATIONS
86 pin TSOP - Type II for x32
V
DD
DQ0
V
DD
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
DD
Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
DD
DQM0
WE
CAS
RAS
CS
NC
BA0
BA1
A10
A0
A1
A2
DQM2
V
DD
NC
DQ16
V
SS
Q
DQ17
DQ18
V
DD
Q
DQ19
DQ20
V
SS
Q
DQ21
DQ22
V
DD
Q
DQ23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
DQ31
V
DD
Q
DQ30
DQ29
V
SS
Q
DQ28
DQ27
V
DD
Q
DQ26
DQ25
V
SS
Q
DQ24
V
SS
PIN DESCRIPTIONS
A0-A10
A0-A7
BA0, BA1
DQ0 to DQ31
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
DQM0-DQM3
V
dd
Vss
V
ddq
Vss
q
NC
Write Enable
x32 Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
11/06/08
3
IS42VS32200E
PIN CONFIGURATION
PACKAGE CODE: B 90 BALL FBGA (Top View) (8.00 mm x 13.00 mm Body, 0.8 mm Ball Pitch)
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
PIN DESCRIPTIONS
A0-A10
A0-A7
BA0, BA1
DQ0 to DQ31
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
DQM0-DQM3
V
dd
Vss
V
ddq
Vss
q
NC
Write Enable
x32 Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
DQ26 DQ24
VSS
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC
A2
A10
NC
BA0
CAS
VDD
DQ6
DQ1
DQ16 VSSQ
DQM2 VDD
A0
BA1
CS
A1
NC
RAS
DQ28 VDDQ VSSQ
VSSQ DQ27 DQ25
VSSQ DQ29 DQ30
VDDQ DQ31
VSS DQM3
A4
A7
CLK
DQM1
A5
A8
CKE
NC
NC
A3
A6
NC
A9
NC
VSS
WE
DQM0
DQ7 VSSQ
DQ5 VDDQ
DQ3 VDDQ
VDDQ DQ8
VSSQ DQ10 DQ9
VSSQ DQ12 DQ14
DQ11 VDDQ VSSQ
DQ13 DQ15
VSS
VDDQ VSSQ DQ4
VDD
DQ0
DQ2
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
11/06/08
IS42VS32200E
PIN FUNCTIONS
Symbol
A0-A10
Pin No. (TSOP)
25 to 27
60 to 66
24
Type
Input Pin
Function (In Detail)
Address Inputs: A0-A10 are sampled during the ACTIVE
command (row-address A0-A10) and READ/WRITE command (A0-A7
with A10 defining auto precharge) to select one location out of the memory array
in the respective bank. A10 is sampled during a PRECHARGE command to deter-
mine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE
or PRECHARGE command is being applied.
CAS,
in conjunction with the
RAS
and
WE,
forms the device command. See the
"Command Truth Table" for details on device commands.
The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE
is LOW, the device will be in either power-down mode, clock suspend mode, or self
refresh mode. CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when
CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when
CS is HIGH.
DQ0 to DQ31 are DQ pins. DQ through these pins can be controlled in byte units
using the DQM0-DQM3 pins
BA0, BA1
CAS
CKE
22,23
18
67
Input Pin
Input Pin
Input Pin
CLK
CS
68
20
Input Pin
Input Pin
DQ0 to 2, 4, 5, 7, 8, 10,11,13
DQ31 74,76,77,79,80,82,83,85
45,47,48,50,51,53,54,56
31,33,34,36,37,39,40,42
DQM0
16,28,59,71
DQM3
DQ Pin
Input Pin
DQMx control thel ower and upper bytes of the DQ buffers. In read mode,
the output buffers are place in a High-Z state. During a WRITE cycle the input data
is masked. When DQMx is sampled HIGH and is an input mask signal for write
accesses and an output enable signal for read accesses. DQ0 through DQ7 are
controlled by DQM0. DQ8 throughDQ15 are controlled by DQM1. DQ16 through
DQ23 are controlled by DQM2. DQ24 through DQ31 are controlled by DQM3.
RAS,
in conjunction with
CAS
and
WE,
forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
WE,
in conjunction with
RAS
and
CAS,
forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
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