K4H510438C-LA2 datasheet, PDF - EEWORLD Datasheet

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K4H510438C-LA2: Description512Mb C-die DDR SDRAM Specification; File Size360KB，24 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K4H510438C-LA2 Overview

512Mb C-die DDR SDRAM Specification

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DDR SDRAM 512Mb C-die (x4, x8, x16)

DDR SDRAM

512Mb C-die DDR SDRAM Specification

66 TSOP-II with Pb-Free

(RoHS compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 1.1 June. 2005

DDR SDRAM 512Mb C-die (x4, x8, x16)

Table of Contents

DDR SDRAM

1.0 Key Features .............................................................................................................................. 4

2.0 Ordering Information ................................................................................................................ 4

3.0 Operating Frequencies............................................................................................................... 4

4.0 Pin Description .......................................................................................................................... 5

5.0 Package Physical Dimension ................................................................................................... 6

6.0 Block Diagram (64Mbit x4 / 32Mbit x8 I/O x4 Banks) ............................................................... 7

7.0 Input/Output Function Description ........................................................................................... 8

8.0 Command Truth Table ............................................................................................................... 9

9.0 General Description...................................................................................................................10

10.0 Absolute Maximum Rating .....................................................................................................10

11.0 DC Operating Conditions ........................................................................................................10

12.0 DDR SDRAM Spec Items & Test Conditions .........................................................................11

13.0 Input/Output Capacitance ......................................................................................................11

14.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A ......................................................12

15.0 DDR SDRAM IDD spec table ..................................................................................................13

16.0 AC Operating Conditions .......................................................................................................14

17.0 AC Overshoot/Undershoot specification for Address and Control Pins ...........................14

18.0 Overshoot/Undershoot specification for Data, Strobe and Mask Pins...............................15

19.0 AC Timming Parameters & Specifications ...........................................................................16

20.0 System Characteristics for DDR SDRAM ............................................................................. 17

21.0 Component Notes ................................................................................................................... 18

22.0 System Notes ..........................................................................................................................20

23.0 IBIS : I/V Characteristics for Input and Output Buffers ........................................................21

Rev. 1.1 June. 2005

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