PALCE20V8Q-7JC datasheet, PDF - EEWORLD Datasheet

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PALCE20V8Q-7JC: DescriptionEE CMOS 24-Pin Universal Programmable Array Logic; File Size122KB，16 Pages; ManufacturerAMD; Websitehttp://www.amd.com

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PALCE20V8Q-7JC Overview

EE CMOS 24-Pin Universal Programmable Array Logic

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FINAL

COM’L: H-5/7/10/15/25, Q-10/15/25

IND: H-15/25, Q-20/25

PALCE20V8 Family

EE CMOS 24-Pin Universal Programmable Array Logic

DISTINCTIVE CHARACTERISTICS

Pin and function compatible with all GAL

Advanced

Micro

Devices

Peripheral Component Interconnect (PCI)

20V8/As

Electrically erasable CMOS technology pro-

vides reconfigurable logic and full testability

High-speed CMOS technology

— 5-ns propagation delay for “-5” version

— 7.5-ns propagation delay for “-7” version

Direct plug-in replacement for a wide range of

24-pin PAL devices

Programmable enable/disable control

Outputs individually programmable as

registered or combinatorial

compliant

Preloadable output registers for testability

Automatic register reset on power-up

Cost-effective 24-pin plastic SKINNYDIP and

28-pin PLCC packages

Extensive third-party software and programmer

support through FusionPLD partners

Fully tested for 100% programming and func-

tional yields and high reliability

Programmable output polarity

5-ns version utilizes a split leadframe for

improved performance

GENERAL DESCRIPTION

The PALCE20V8 is an advanced PAL device built with

low-power, high-speed, electrically-erasable CMOS

technology. Its macrocells provide a universal device

architecture. The PALCE20V8 is fully compatible with

the GAL20V8 and can directly replace PAL20R8 series

devices and most 24-pin combinatorial PAL devices.

Device logic is automatically configured according to the

user’s design specification. A design is implemented

using any of a number of popular design software pack-

ages, allowing automatic creation of a programming file

based on Boolean or state equations. Design software

also verifies the design and can provide test vectors for

the finished device. Programming can be accomplished

on standard PAL device programmers.

The PALCE20V8 utilizes the familiar sum-of-products

(AND/OR) architecture that allows users to implement

complex logic functions easily and efficiently. Multiple

levels of combinatorial logic can always be reduced to

sum-of-products form, taking advantage of the very

wide input gates available in PAL devices. The equa-

tions are programmed into the device through floating-

gate cells in the AND logic array that can be erased

electrically.

The fixed OR array allows up to eight data product terms

per output for logic functions. The sum of these products

feeds the output macrocell. Each macrocell can be

programmed as registered or combinatorial with an

active-high or active-low output. The output configura-

tion is determined by two global bits and one local bit

controlling four multiplexers in each macrocell.

BLOCK DIAGRAM

– I

CLK/I

Programmable AND Array

40 x 64

Input

Mux.

MACRO

Input

Mux.

OE/I

Publication#

16491

Rev.

Issue Date:

February 1996

I/O

16491D-1

Amendment

2-155

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