W83977EF-AW /W83977EG-AW
NUVOTON
ISA I/O
W83977EF-AW
W83977EG-AW
-I -
Publication Release Date: January, 2010
Revision 1.5
W83977EF-AW /W83977EG-AW
TABLES OF CONTENTS
1. GENERAL DESCRIPTION
.............................................................................................................................1
2. FEATURES
.......................................................................................................................................................2
3. PIN CONFIGURATION
...................................................................................................................................5
4. PIN DESCRIPTION.........................................................................................................................................6
4.1 H
OST
I
NTERFACE
..........................................................................................................................................6
4.2 G
ENERAL
P
URPOSE
I/O P
ORT
......................................................................................................................8
4.3 S
ERIAL
P
ORT
I
NTERFACE
..............................................................................................................................9
4.4 I
NFRARED
I
NTERFACE
.................................................................................................................................10
4.5 M
ULTI
-M
ODE
P
ARALLEL
P
ORT
...................................................................................................................11
4.6 FDC I
NTERFACE
.........................................................................................................................................16
4.7 KBC I
NTERFACE
.........................................................................................................................................18
4.8 POWER PINS
...........................................................................................................................................18
4.9 ACPI I
NTERFACE
........................................................................................................................................18
5. FDC FUNCTIONAL DESCRIPTION
...........................................................................................................19
5.1 W83977EF-AW/EG FDC
.........................................................................................................................19
5.1.1 AT interface........................................................................................................................................19
5.1.2 FIFO (Data)
........................................................................................................................................19
5.1.3 Data Separator
..................................................................................................................................20
5.1.4 Write Precompensation....................................................................................................................20
5.1.5 Perpendicular Recording Mode
......................................................................................................20
5.1.6 FDC Core
...........................................................................................................................................21
5.1.7 FDC Commands................................................................................................................................21
5.2 R
EGISTER
D
ESCRIPTIONS
...........................................................................................................................33
5.2.1 Status Register A (SA Register) (Read base address + 0)
........................................................33
5.2.2 Status Register B (SB Register) (Read base address + 1)
........................................................35
5.2.3 Digital Output Register (DO Register) (Write base address + 2)...............................................37
5.2.4 Tape Drive Register (TD Register) (Read base address + 3)....................................................37
5.2.5 Main Status Register (MS Register) (Read base address + 4)..................................................38
5.2.6 Data Rate Register (DR Register) (Write base address + 4)
.....................................................38
5.2.7 FIFO Register (R/W base address + 5)
.........................................................................................40
5.2.8 Digital Input Register (DI Register) (Read base address + 7)....................................................42
5.2.9 Configuration Control Register (CC Register) (Write base address + 7)
.................................43
6. UART PORT
...................................................................................................................................................45
6.1 U
NIVERSAL
A
SYNCHRONOUS
R
ECEIVER
/T
RANSMITTER
(UART A, UART B)..........................................45
6.2 R
EGISTER
A
DDRESS
...................................................................................................................................45
6.2.1 UART Control Register (UCR) (Read/Write)
................................................................................45
6.2.2 UART Status Register (USR) (Read/Write)
..................................................................................48
-II -
Publication Release Date: January, 2010
Revision 1.5
W83977EF-AW /W83977EG-AW
6.2.3 Handshake Control Register (HCR) (Read/Write)
.......................................................................48
6.2.4 Handshake Status Register (HSR) (Read/Write).........................................................................49
6.2.5 UART FIFO Control Register (UFR) (Write only)
.........................................................................50
6.2.6 Interrupt Status Register (ISR) (Read only)
..................................................................................51
6.2.7 Interrupt Control Register (ICR) (Read/Write)
..............................................................................52
6.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write)
..........................................................52
6.2.9 User-defined Register (UDR) (Read/Write)
..................................................................................52
7. PARALLEL PORT
........................................................................................................................................54
7.1 P
RINTER
I
NTERFACE
L
OGIC
........................................................................................................................54
7.2 E
NHANCED
P
ARALLEL
P
ORT
(EPP)
...........................................................................................................55
7.2.1 Data Swapper
....................................................................................................................................56
7.2.2 Printer Status Buffer
.........................................................................................................................56
7.2.3 Printer Control Latch and Printer Control Swapper
.....................................................................57
7.2.4 EPP Address Port
.............................................................................................................................57
7.2.5 EPP Data Port 0-3
............................................................................................................................58
7.2.6 Bit Map of Parallel Port and EPP Registers..................................................................................58
7.2.7 EPP Pin Descriptions
.......................................................................................................................59
7.2.8 EPP Operation...................................................................................................................................59
7.3 E
XTENDED
C
APABILITIES
P
ARALLEL
(ECP) P
ORT
.....................................................................................60
7.3.1
ECP Register and Mode Definitions
.........................................................................................60
7.3.2 Data and ecpAFifo Port....................................................................................................................61
7.3.3 Device Status Register (DSR).........................................................................................................61
7.3.4 Device Control Register (DCR).......................................................................................................62
7.3.5 CFIFO (Parallel Port Data FIFO) Mode = 010
..............................................................................63
7.3.6 ECPDFIFO (ECP Data FIFO) Mode = 011
...................................................................................63
7.3.7 TFIFO (Test FIFO Mode) Mode = 110...........................................................................................63
7.3.8 CNFGA (Configuration Register A) Mode = 111
..........................................................................63
7.3.9 CNFGB (Configuration Register B) Mode = 111
..........................................................................63
7.3.10 ECR (Extended Control Register) Mode = all.............................................................................64
7.3.11 Bit Map of ECP Port Registers......................................................................................................65
7.3.12 ECP Pin Descriptions
.....................................................................................................................66
7.3.13 ECP Operation
................................................................................................................................67
7.3.14 FIFO Operation
...............................................................................................................................67
7.3.15 DMA Transfers
................................................................................................................................68
7.3.16 Programmed I/O (NON-DMA) Mode............................................................................................68
7.4 E
XTENSION
FDD M
ODE
(EXTFDD)
..........................................................................................................68
7.5 E
XTENSION
2FDD M
ODE
(EXT2FDD)......................................................................................................68
8.KEYBOARD CONTROLLER
........................................................................................................................69
8.1 O
UTPUT
B
UFFER
.........................................................................................................................................69
8.2 I
NPUT
B
UFFER
.............................................................................................................................................69
8.3 S
TATUS
R
EGISTER
......................................................................................................................................70
8.4 C
OMMANDS
.................................................................................................................................................71
8.5 H
ARDWARE
GATEA20/K
EYBOARD
R
ESET
C
ONTROL
L
OGIC
...................................................................72
-III -
Publication Release Date: January, 2010
Revision 1.5
W83977EF-AW /W83977EG-AW
8.5.1 KB Control Register (Logic Device 5, CR-F0)
..............................................................................73
8.5.2
Port 92 Control Register (Default Value = 0x24)
....................................................................73
8.6 O
N
N
OW
/ S
ECURITY
K
EYBOARD AND
M
OUSE
W
AKE
-U
P
...........................................................................74
8.6.1 Keyboard Wake-Up Function
..........................................................................................................74
8.6.2 Keyboard Password Wake-Up Function
.......................................................................................74
8.6.3 Mouse Wake-Up Function
...............................................................................................................74
9. GENERAL PURPOSE I/O
............................................................................................................................75
9.1 B
ASIC
I/O
FUNCTIONS
...................................................................................................................................77
9.2 A
LTERNATE
I/O F
UNCTIONS
.........................................................................................................................79
9.2.1 Interrupt Steering .................................................................................................................................79
9.2.2 Watch Dog Timer Output .....................................................................................................................80
9.2.3 Power LED ...........................................................................................................................................80
9.2.4 General Purpose Address Decoder ......................................................................................................80
10. PLUG AND PLAY CONFIGURATION
.....................................................................................................81
10.1 C
OMPATIBLE
P
N
P .......................................................................................................................................81
10.1.1 Extended Function Registers ..............................................................................................................81
10.1.2 Extended Functions Enable Registers (EFERs) .................................................................................82
10.1.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs) ...............82
10.2 C
ONFIGURATION
S
EQUENCE
.......................................................................................................................82
10.2.1 Enter the extended function mode.......................................................................................................82
10.2.2 Configurate the configuration registers .............................................................................................83
10.2.3 Exit the extended function mode .........................................................................................................83
10.2.4 Software programming example.........................................................................................................83
11. ACPI REGISTERS FEATURES
................................................................................................................84
12. CONFIGURATION REGISTER
.................................................................................................................85
12.1 C
HIP
(G
LOBAL
) C
ONTROL
R
EGISTER
.......................................................................................................85
12.2 L
OGICAL
D
EVICE
0 (FDC)
.......................................................................................................................91
12.3 L
OGICAL
D
EVICE
1 (P
ARALLEL
P
ORT
)......................................................................................................95
12.4 L
OGICAL
D
EVICE
2 (UART A)¢)
..............................................................................................................95
12.5 L
OGICAL
D
EVICE
3 (UART B)
..................................................................................................................96
12.6 L
OGICAL
D
EVICE
5 (KBC)
........................................................................................................................99
12.7 L
OGICAL
D
EVICE
7 (GP I/O P
ORT
I)
......................................................................................................100
12.8 L
OGICAL
D
EVICE
8 (GP I/O P
ORT
II)
.....................................................................................................104
12.9 L
OGICAL
D
EVICE
A (ACPI).....................................................................................................................109
13.SPECIFICATIONS
......................................................................................................................................116
13.1 A
BSOLUTE
M
AXIMUM
R
ATINGS
...............................................................................................................116
13.2 DC CHARACTERISTICS
....................................................................................................................116
13.3 AC C
HARACTERISTICS
...........................................................................................................................120
13.3.1 FDC: Data rate = 1 MB, 500 KB, 300 KB, 250 KB/sec.
..........................................................120
13.3.2 UART/Parallel Port
.......................................................................................................................122
-IV -
Publication Release Date: January, 2010
Revision 1.5
W83977EF-AW /W83977EG-AW
13.3.3 Parallel Port Mode Parameters...................................................................................................122
13.3.4 EPP Data or Address Read Cycle Timing Parameters
...........................................................123
13.3.5 EPP Data or Address Write Cycle Timing Parameters
...........................................................124
13.3.6 Parallel Port FIFO Timing Parameters.......................................................................................125
13.3.7 ECP Parallel Port Forward Timing Parameters........................................................................125
13.3.8 ECP Parallel Port Reverse Timing Parameters
.......................................................................125
13.3.9 KBC Timing Parameters
..............................................................................................................126
13.3.10 GPIO Timing Parameters
.........................................................................................................127
13.3.11 Keyboard/Mouse Timing Parameters
.....................................................................................127
14. TIMING WAVEFORMS
.............................................................................................................................128
14.1 FDC
........................................................................................................................................................128
14.2 UART/P
ARALLEL
....................................................................................................................................129
14.2.1 Modem Control Timing................................................................................................................130
14.3 P
ARALLEL
P
ORT
.....................................................................................................................................131
14.3.1 Parallel Port Timing
.....................................................................................................................131
14.3.2 EPP Data or Address Read Cycle (EPP Version 1.9)............................................................132
14.3.3 EPP Data or Address Write Cycle (EPP Version 1.9)
............................................................133
14.3.4 EPP Data or Address Read Cycle (EPP Version 1.7)............................................................134
14.3.5 EPP Data or Address Write Cycle (EPP Version 1.7)
............................................................135
14.3.6 Parallel Port FIFO Timing
...........................................................................................................135
14.3.7 ECP Parallel Port Forward Timing
............................................................................................136
14.3.8 ECP Parallel Port Reverse Timing
............................................................................................136
14.4 KBC
........................................................................................................................................................137
14.4.1 Write Cycle Timing
......................................................................................................................137
14.4.2 Read Cycle Timing
......................................................................................................................137
14.4.3 Send Data to K/B
.........................................................................................................................137
14.4.4 Receive Data from K/B
...............................................................................................................138
14.4.5 Input Clock
....................................................................................................................................138
14.4.6 Send Data to Mouse....................................................................................................................138
14.4.7 Receive Data from Mouse..........................................................................................................138
14.5 GPIO W
RITE
T
IMING
D
IAGRAM
..............................................................................................................139
14.6 M
ASTER
R
ESET
(MR) T
IMING
................................................................................................................139
14.7 K
EYBOARD
/M
OUSE
W
AKE
-
UP
T
IMING
....................................................................................................139
14.8
ISA R
EAD
T
IMING
....................................................................................................................................140
14.9 ISA W
RITE
T
IMING
...................................................................................................................................141
15. APPLICATION CIRCUITS........................................................................................................................142
15.1 P
ARALLEL
P
ORT
E
XTENSION
FDD.........................................................................................................142
15.2 P
ARALLEL
P
ORT
E
XTENSION
2FDD.......................................................................................................143
15.3 F
OUR
FDD M
ODE
...................................................................................................................................144
16. ORDERING INFORMATION ..................................................................................................................144
17. TOP MARKING SPECIFICATIONS........................................................................................................144
-V -
Publication Release Date: January, 2010
Revision 1.5
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