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XA Spartan-3 Automotive FPGA Family:
Introduction and Ordering Information
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DS314 (v1.3) June 18, 2009
Product Specification
Summary
The Xilinx® Automotive (XA) Spartan®-3 family of Field-Programmable Gate Arrays meets the needs of high-volume,
cost-sensitive automotive electronic applications. The five-member family offers densities ranging from 50,000 to 1.5 million
system gates, as shown in
Table 1.
Introduction
XA devices are available in both extended-temperature
Q-grade (–40
°
C to +125
°
C
T
J
) and I-grade (–40
°
C to
+100
°
C
T
J
) and are qualified to the industry-recognized
AEC-Q100 standard.
The XA Spartan-3 family builds on the success of the earlier
XA Spartan-IIE family by increasing the amount of logic
resources, the capacity of internal RAM, the total number of
I/Os, and the overall level of performance as well as by
improving clock management functions. These Spartan-3
enhancements, combined with advanced process
technology, deliver more functionality and bandwidth per
dollar than was previously possible, setting new standards
in the programmable logic industry.
Because of their exceptionally low cost, Spartan-3 FPGAs
are ideally suited to a wide range of advanced automotive
electronics modules and systems ranging from the latest
driver assistance and infotainment systems to instrument
clusters and gateways.
The Spartan-3 family is a flexible alternative to ASICs,
ASSPs, and microcontrollers. FPGAs avoid the high initial
NREs, the lengthy development cycles, and problems with
obsolescence. Also, FPGA programmability permits design
upgrades in the field with no hardware replacement
necessary.
Table 1:
Summary of Spartan-3 FPGA Attributes
System
Gates
50K
200K
400K
1M
1.5M
Logic
Cells
1,728
4,320
8,064
17,280
29,952
CLB Array
(One CLB = Four Slices)
Rows
16
24
32
48
64
Columns Total CLBs
12
20
28
40
52
192
480
896
1,920
3,328
Features
•
AEC-Q100 device qualification and full PPAP
documentation support available in both extended
temperature Q-grade and I-grade
Guaranteed to meet full electrical specification over the
T
J
= –40
°
C to +125
°
C temperature range
Revolutionary 90-nanometer process technology
Low cost, high-performance logic solution for
high-volume, automotive applications
♦
•
•
•
Three power rails: for core (1.2V), I/Os (1.2V to
3.3V), and auxiliary purposes (2.5V)
Up to 487 I/O pins
622 Mb/s data transfer rate per I/O
Eighteen single-ended signal standards
Eight differential signal standards including LVDS
Termination by Digitally Controlled Impedance
Signal swing ranging from 1.14V to 3.45V
Double Data Rate (DDR) support
Abundant logic cells with shift register capability
Wide multiplexers
•
SelectIO™ interface signaling
♦
♦
♦
♦
♦
♦
♦
•
Logic resources
♦
♦
Device
XA3S50
XA3S200
XA3S400
XA3S1000
XA3S1500
Distributed
RAM (bits
1
)
12K
30K
56K
120K
208K
Block RAM
(bits
1
)
72K
216K
288K
432K
576K
Dedicated
Multipliers
4
12
16
24
32
DCMs
2
4
4
4
4
Maximum
User I/O
124
173
264
333
487
Maximum
Differential
I/O Pairs
56
76
116
149
221
Notes:
1. By convention, one Kb is equivalent to 1,024 bits.
© 2004–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium in the U.S. and other jurisdictions. All other trademarks are the property of their
respective owners.
DS314 (v1.3) June 18, 2009
Product Specification
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R
Introduction and Ordering Information
elements that can be used as flip-flops or latches.
CLBs can be programmed to perform a wide variety of
logical functions as well as to store data.
•
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. Each IOB supports bidirectional data flow plus
3-state operation. Twenty-six different signal standards,
including eight high-performance differential standards,
are available as shown in
Table 2.
Double Data-Rate
(DDR) registers are included. The Digitally Controlled
Impedance (DCI) feature provides automatic on-chip
terminations, simplifying board designs.
Block RAM provides data storage in the form of 18-Kbit
dual-port blocks.
Multiplier blocks accept two 18-bit binary numbers as
inputs and calculate the product.
Digital Clock Manager (DCM) blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase shifting clock
signals.
♦
♦
♦
Fast look-ahead carry logic
Dedicated 18 x 18 multipliers
JTAG logic compatible with IEEE 1149.1/1532
Up to 576 Kbits of total block RAM
Up to 208 Kbits of total distributed RAM
Clock skew elimination
Frequency synthesis
High-resolution phase shifting
Maximum clock frequency 125 MHz
•
•
•
•
SelectRAM™ hierarchical memory
♦
♦
•
Digital Clock Manager (up to four DCMs)
♦
♦
♦
♦
•
Fully supported by Xilinx ISE® software development
system
♦
Synthesis, mapping, placement and routing
•
•
•
MicroBlaze™ processor, CAN, LIN, MOST, and other
cores
Pb-free packaging options
Xilinx and all of our production partners are qualified to
ISO-TS16949
Please refer to the Spartan-3 complete data sheet (DS099)
for a full product description, AC and DC specifications, and
package pinout descriptions
Architectural Overview
The Spartan-3 family architecture consists of five
fundamental programmable functional elements:
•
Configurable Logic Blocks (CLBs) contain RAM-based
Look-Up Tables (LUTs) to implement logic and storage
These elements are organized as shown in
Figure 1.
A ring
of IOBs surrounds a regular array of CLBs. The XA3S50
has a single column of block RAM embedded in the array.
Those devices ranging from the XA3S200 to the XA3S1500
have two columns of block RAM. Each column is made up
of several 18 Kbit RAM blocks; each block is associated
with a dedicated multiplier. The DCMs are positioned at the
ends of the block RAM columns.
The Spartan-3 family features a rich network of traces and
switches that interconnect all five functional elements,
transmitting signals among them. Each functional element
has an associated switch matrix that permits multiple
connections to the routing.
DS314 (v1.3) June 18, 2009
Product Specification
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Introduction and Ordering Information
DS314-1_01_100808
Notes:
1.
The XA3S50 has only the block RAM column on the far left.
Figure 1:
Spartan-3 Family Architecture
Configuration
Spartan-3 FPGAs are programmed by loading configuration
data into robust static memory cells that collectively control
all functional elements and routing resources. Before
powering on the FPGA, configuration data is stored
externally in a PROM or some other nonvolatile medium
either on or off the board. After applying power, the
configuration data is written to the FPGA using any of five
different modes: Master Parallel, Slave Parallel, Master
Serial, Slave Serial and Boundary Scan (JTAG). The Master
and Slave Parallel modes use an 8-bit-wide SelectMAP
port.
.
I/O Capabilities
The SelectIO feature of Spartan-3 devices supports 18
single-ended standards and eight differential standards as
listed in
Table 2.
Many standards support the DCI feature,
which uses integrated terminations to eliminate unwanted
signal reflections.
Table 3
shows the number of user I/Os as
well as the number of differential I/O pairs available for each
device/package combination.
DS314 (v1.3) June 18, 2009
Product Specification
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Introduction and Ordering Information
Table 2:
Signal Standards Supported by the Spartan-3 Family
Standard
Category
Description
V
CCO
(V)
Class
Symbol
DCI
Option
Single-Ended
GTL
HSTL
Gunning Transceiver Logic
High-Speed Transceiver Logic
N/A
1.5
1.8
Terminated
Plus
I
III
I
II
III
GTL
GTLP
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
LVCMOS12
LVCMOS15
LVCMOS18
LVCMOS25
LVCMOS33
LVTTL
PCI33_3
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
No
No
Yes
No
Yes
Yes
LVCMOS
Low-Voltage CMOS
1.2
1.5
1.8
2.5
3.3
N/A
N/A
N/A
N/A
N/A
N/A
33 MHz
N/A (±6.7 mA)
N/A (±13.4 mA)
I
II
LVTTL
PCI
SSTL
Low-Voltage Transistor-Transistor Logic
Peripheral Component Interconnect
Stub Series Terminated Logic
3.3
3.0
1.8
2.5
Differential
LDT
(ULVDS)
LVDS
Lightning Data Transport
(HyperTransport™)
Low-Voltage Differential Signaling
2.5
N/A
Standard
Bus
Extended Mode
LDT_25
LVDS_25
BLVDS_25
LVDSEXT_25
LVPECL_25
RSDS_25
DIFF_HSTL_II_18
DIFF_SSTL2_II
No
Yes
No
Yes
No
No
Yes
Yes
LVPECL
RSDS
HSTL
SSTL
Low-Voltage Positive Emitter-Coupled
Logic
Reduced-Swing Differential Signaling
Differential High-Speed Transceiver Logic
Differential Stub Series Terminated Logic
2.5
2.5
1.8
2.5
N/A
N/A
II
II
DS314 (v1.3) June 18, 2009
Product Specification
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4
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Introduction and Ordering Information
Table 3:
Spartan-3 XA I/O Chart
Available User I/Os and Differential (Diff) I/O Pairs
VQG100
Device
XA3S50
XA3S200
XA3S400
XA3S1000
XA3S1500
Grade
I,Q
I,Q
I,Q
I,Q
I
User
63
63
-
-
-
Diff
29
29
-
-
-
TQG144
User
-
97
-
-
-
Diff
-
46
-
-
-
PQG208
User
124
141
141
-
-
Diff
56
62
62
-
-
FTG256
User
-
173
173
173
-
Diff
-
76
76
76
-
FGG456
User
-
-
264
333
333
Diff
-
-
116
149
149
FGG676
User
-
-
-
-
487
Diff
-
-
-
-
221
Notes:
1. All device options listed in a given package column are pin-compatible.
DC Specifications
Table 4:
General Recommended Operating Conditions
Symbol
Description
I-Grade
Junction temperature
Internal supply voltage
Q-Grade
Min
–40
–40
1.140
1.140
2.375
-
–0.3
–0.3
–0.3
Nom
25
25
1.200
-
2.500
-
-
-
-
Max
100
125
1.260
3.450
2.625
10
3.75
Units
°C
°C
V
V
V
mV/ms
V
V
V
T
J
V
CCINT
V
CCO(1)
V
CCAUX
V
IN
Output driver supply voltage
Auxiliary supply voltage
Voltage applied to all User I/O
pins and Dual-Purpose pins
relative to GND
Voltage applied to all
Dedicated pins relative to
GND
Δ
V
CCAUX(2)
Voltage variance on VCCAUX when using a DCM
V
CCO
= 3.3V
V
CCO
< 2.5V
V
CCO
+0.3
V
CCAUX
+
0.3
Notes:
1.
2.
The V
CCO
range given here spans the lowest and highest operating voltages of all supported I/O standards. The recommended V
CCO
range
specific to each of the single-ended I/O standards is given in Table 34 of
DS099,
and that specific to the differential standards is given in
Table 36 of
DS099.
Only during DCM operation is it recommended that the rate of change of V
CCAUX
not exceed 10 mV/ms.
DS314 (v1.3) June 18, 2009
Product Specification
www.xilinx.com
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