SRAM
Austin Semiconductor, Inc.
32K x 8 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
•SMD 5962-88662
•MIL-STD-883
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MT5C2568
PIN ASSIGNMENT
(Top View)
28-PIN SOJ (DCJ)
28-Pin DIP (C, CW)
V
CC
WE\
A13
A8
A9
A11
OE\
A10
CE\
DQ8
DQ7
DQ6
DQ5
DQ4
32-Pin LCC (ECW)
4 3 2 1 32 31 30
FEATURES
•
•
•
•
•
•
•
Access Times: 12, 15, 20, 25, 35, 45, 55, 70, & 100ns
Battery Backup: 2V data retention
Low power standby
High-performance, low-power CMOS double-metal process
Single +5V (+10%) Power Supply
Easy memory expansion with CE\
All inputs and outputs are TTL compatible
A6
A5
A4
A3
A2
A1
A0
NC
DQ1
5
6
7
8
9
10
11
12
13
A7
A12
A14
NC
V
CC
WE\
A13
29
28
27
26
25
24
23
22
21
A8
A9
A11
NC
OE\
A10
CE\
DQ8
DQ7
14 15 16 17 18 19 20
OPTIONS
•
Timing
12ns access
1
15ns access
1
20ns access
25ns access
35ns access
45ns access
55ns access
2
70ns access
2
100ns access
•
Package(s)
3
Ceramic DIP (300 mil)
Ceramic DIP (600 mil)
Ceramic LCC (28 leads)
Ceramic LCC (32 leads)
Ceramic LCC
Ceramic Flat Pack
Ceramic SOJ
•
Operating Temperature Ranges
Military -55
o
C to +125
o
C
Industrial -40
o
C to +85
o
C
• 2V data retention/low power
MARKING
-12
-15
-20
-25
-35
-45
-55
-70
-100
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28-Pin Flat Pack (F)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE\
A13
A8
A9
A11
OE\
A10
CE\
DQ8
DQ7
DQ6
DQ5
DQ4
3 2 1 28 27
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
4
5
6
7
8
9
10
11
12
A7
A12
A14
V
CC
WE\
26
25
24
23
22
21
20
19
18
DQ2
DQ3
V
SS
NC
DQ4
DQ5
DQ6
28-Pin LCC (EC)
A13
A8
A9
A11
OE\
A10
CE\
DQ8
DQ7
13 14 15 16 17
C
CW
EC
ECW
ECJ
F
DCJ
No. 108
No. 110
No. 204
No. 208
No. 605
No. 302
No. 500
GENERAL DESCRIPTION
The Austin Semiconductor SRAM family employs
high-speed, low power CMOS designs using a four-transistor
memory cell. These SRAMs are fabricated using double-layer
metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications, Aus-
tin Semiconductor offers chip enable (CE\) and output enable
(OE\) capability. These enhancements can place the outputs in
High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is accom-
plished when WE\ remains HIGH and CE\ and OE\ go LOW.
The device offers a reduced power standby mode when dis-
abled. This allows system designs to achieve low standby
power requirements.
The “L” version provides a battery backup/low volt-
age data retention mode, offering 2mW maximum power dissi-
pation at 2 volts. All devices operate from a single +5V power
supply and all inputs and outputs are fully TTL compatible.
XT
IT
L
NOTES:
1. -12 available in IT only.
2. Electrical characteristics identical to those provided for the
45ns access devices.
3. Plastic SOJ (DJ Package) is available on the AS5C2568 datasheet.
For more products and information
please visit our web site at
www.austinsemiconductor.com
MT5C2568
Rev. 3.0 10/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
DQ3
V
SS
DQ4
DQ5
DQ6
SRAM
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
A0
Vcc
MT5C2568
DECODER
256 x 1024
MEMORY ARRAY
GND
A14
I/O0
I/O
DATA
CIRCUIT
I/O7
COLUMN I/O
9A128-1
CE\
OE\
CONTROL
CIRCUIT
WE\
TRUTH TABLE
MODE
STANDBY
READ
READ
WRITE
OE\
X
L
H
X
CE\
H
L
L
L
WE\
X
H
H
L
DQ
HIGH-Z
Q
HIGH-Z
D
POWER
STANDBY
ACTIVE
ACTIVE
ACTIVE
MT5C2568
Rev. 3.0 10/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
SRAM
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Input or DQ Relative
to Vss..................................................................-0.5V to Vcc +0.5V
Voltage on Vcc Supply Relative to Vss.......................-1V to +7V
Storage Temperature..............................................-65
o
C to +150
o
C
Power Dissipation.......................................................................1W
Short Circuit Output Current.................................................50mA
Lead Temperature (soldering 10 seconds)........................+260
o
C
Max. Junction Temperature.................................................+175
o
C
MT5C2568
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55
o
C < T
C
< 125
o
C or -40
o
C to +85
o
C; V
CC
= 5.0V +10%)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
0V<V
IN
<V
CC
Output(s) disabled
0V<V
OUT
<V
CC
I
OH
= -4.0mA
I
OL
= 8.0mA
CONDITIONS
CE\<V
IL
; Vcc = MAX
f = MAX = 1/ RC (MIN)
Output Open
TTL
Power Supply
Current: Standby
CMOS
CE\<V
IH
; Outputs Open
Vcc = MAX
CE\>Vcc-0.2V; Vcc = MAX
V
IN
<+0.2V or >Vcc-0.2V;
f = 0 Hz, Outputs Open
"L" Version Only
t
CONDITIONS
SYM MIN
V
IH
V
IL
IL
I
ILo
V
OH
V
OL
-12
-15
MAX
-20 -25
MAX
V
CC
+0.5
0.8
10
10
UNITS NOTES
V
V
µA
µA
V
1
1
1
1,2
2.2
-0.5
-10
-10
2.4
0.4
V
DESCRIPTION
Power Supply
Current: Operating
SYM
Icc
-35
-45 UNITS NOTES
mA
3
190 180 170 160 150 150
I
SBT
60
50
40
35
35
35
mA
I
SBC
I
SBC2
20
4
20
4
20
4
20
4
20
4
20
4
mA
mA
CAPACITANCE
PARAMETER
Input Capacitance
Output Capacitance
CONDITIONS
T
A
= 25 C, f = 1MHz
Vcc = 5V
o
SYM
C
IN
C
IO
MAX
11
11
UNITS
pF
pF
NOTES
4
4
MT5C2568
Rev. 3.0 10/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
SRAM
Austin Semiconductor, Inc.
MT5C2568
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55
o
C < T
C
< 125
o
C or -40
o
C to +85
o
C; V
CC
= 5.0V +10%)
DESCRIPTION
READ CYCLE
READ cycle time
Address access time
Chip enable access time
Output hold from address change
Chip enable to output in Low-Z
Chip disable to output in High-Z
Output enable to access time
Output enable to output in Low-Z
SYM
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
AOE
t
LZOE
0
7
12
10
10
0
2
10
8
0
0
7
15
12
12
0
0
12
10
0
0
10
2
2
7
6
0
10
20
15
15
0
0
15
10
0
0
10
-12
-15
-20
MIN MAX MIN MAX MIN MAX
12
12
12
3
3
10
8
0
10
25
20
20
0
0
20
15
0
3
15
15
15
15
3
3
10
10
0
15
35
30
30
0
0
30
20
0
3
35
20
20
20
3
3
15
15
2
35
45
40
40
0
0
40
20
3
3
20
-25
MIN MAX
25
25
25
3
3
35
20
0
20
-35
MIN MAX
35
35
35
3
3
20
20
-45
MIN MAX
45
45
45
UNITS NOTES
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
6, 7
6
7
6, 7
Output disable to output in High-Z t
HZOE
WRITE CYCLE
WRITE cycle time
t
WC
Chip enable to end of write
Address valid to end of write
Address setup time
Address hold from end of write
WRITE pulse width
Data setup time
Data hold time
Write disable to output in Low-Z
Write enable to output in High-Z
t
CW
t
AW
t
AS
t
AH
t
WP
t
DS
t
DH
t
LZWE
t
HZWE
MT5C2568
Rev. 3.0 10/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
SRAM
Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input pulse levels....................................................Vss to 3V
Input rise and fall times.....................................................5ns
Input timing reference level.............................................1.5V
Output reference level......................................................1.5V
Output load.................................................See figures 1 & 2
+5V
480
Q
255
30 pF
Q
255
5 pF
MT5C2568
+5V
480
NOTES
1.
2.
3.
All voltages referenced to V
SS
(GND).
-3V for pulse width < 20ns
I
CC
is dependent on output loading and cycle rates. The
specified value applies with the outputs unloaded, and
f=
1
Hz.
t
RC (MIN)
This parameter is guaranteed but not tested.
Test conditions as specified with the output loading as
shown in Fig. 1 unless otherwise noted.
t
HZCE,
t
HZOE and
t
HZWE are specified with CL = 5pF
as in Fig. 2. Transition is measured ±500mV typical from
steady state voltage, allowing for actual tester RC time
constant.
7.
Fig. 1
OUTPUT LOAD
EQUIVALENT
Fig. 2
OUTPUT LOAD
EQUIVALENT
4.
5.
6.
At any given temperature and voltage condition,
t
HZCE
is less than
t
LZCE, and
t
HZWE is less than
t
LZWE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11.
t
RC = Read Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
V
CC
for Retention Data
CE\ > (V
CC
-0.2V)
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
V
IN
> (V
CC
-0.2V)
or < 0.2V
I
CCDR
1
mA
CONDITIONS
SYM
V
DR
MIN
2
MAX
UNITS
V
NOTES
t
CDR
t
R
0
t
RC
--
ns
ns
4
4, 11
LOW Vcc DATA RETENTION WAVEFORM
V
CC
t
DATA RETENTION MODE
4.5V
CDR
V
DR
V
DR
> 2V
4.5V
t
R
MT5C2568
Rev. 3.0 10/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
4321
4321
4321
4321
321
21
321
321
3
CE\
V
IH
V
IL
321
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876
3311
4325
8765
87654321
21
21
87654321
321
87654321
321
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87654321
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DON’T CARE
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