1. Features
•
Medium-voltage and Standard-voltage Operation
•
•
•
•
•
•
•
•
– 2.7 (V
CC
= 2.7V to 5.5V)
Automotive Temperature Range –40°C to +125°C
User Selectable Internal Organization
– 16K: 2048 x 8 or 1024 x 16
3-wire Serial Interface
Sequential Read Operation
Schmitt Trigger, Filtered Inputs for Noise Suppression
2 MHz Clock Rate (5V) Compatibility
Self-timed Write Cycle (10 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
Lead-Free/Halogen-Free Devices Available
8-lead JEDEC SOIC and 8-lead TSSOP Packages
•
•
Three-wire
Automotive
Temperature
Serial
EEPROM
16K
(2048 x 8 or 1024 x 16)
2. Description
The AT93C86A provides 16384 bits of serial electrically erasable programmable read
only memory (EEPROM), organized as 1024 words of 16 bits each when the ORG pin
is connected to V
CC
and 2048 words of 8 bits each when it is tied to ground. The
device is optimized for use in many automotive applications where low-power and
low-voltage operations are essential. The AT93C86A is available in space saving 8-
lead JEDEC SOIC and 8-lead TSSOP packages.
Table 2-1.
Pin Name
CS
SK
DI
DO
GND
VCC
ORG
DC
AT93C86A
Pin Configuration
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Internal Organization
Don’t Connect
8-lead SOIC
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
DC
ORG
GND
8-lead TSSOP
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
DC
ORG
GND
The AT93C86A is enabled through the Chip Select pin (CS), and accessed via a
three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the
data is clocked out serially on the data output pin DO. The write cycle is completely
self-timed and no separate erase cycle is required before Write. The write cycle is only
enabled when the part is in the Erase/Write Enable state. When CS is brought “high”
following the initiation of a write cycle, the DO pin outputs the Ready/Busy status of
the part. The AT93C86A is available in a 2.7V to 5.5V version.
Rev. 5096E–SEEPR–1/08
Absolute Maximum Ratings*
Operating Temperature..................................–55°C to +125°C
Storage Temperature .....................................–65°C to +150°C
Voltage on any Pin
with Respect to Ground .................................... –1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only, and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Figure 2-1.
Block Diagram
Vcc
GND
MEMORY ARRAY
ORG
2048 x 8
OR
1024 x 16
ADDRESS
DECODER
DATA
REGISTER
DI
MODE
DECODE
LOGIC
OUTPUT
BUFFER
CS
SK
CLOCK
GENERATOR
DO
Note:
When the ORG pin is connected to Vcc, the x 16 organization is selected. When it is connected to ground, the x 8 organization
is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1
Meg ohm pullup, then the x 16 organization is selected.
Table 2-2.
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25°C, f = 1.0 MHz, V
CC
= +5.0V (unless otherwise noted)
Symbol
C
OUT
C
IN
Note:
Test Conditions
Output Capacitance (DO)
Input Capacitance (CS, SK, DI)
1. This parameter is characterized and is not 100% tested.
Max
5
5
Units
pF
pF
Conditions
V
OUT
= 0V
V
IN
= 0V
2
AT93C86A
5096E–SEEPR–1/08
AT93C86A
Table 2-3.
DC Characteristics
Applicable over recommended operating range from: T
A
=
–
40°C to +125°C, V
CC
= +2.7V to +5.5V (unless otherwise
noted)
Symbol
V
CC1
V
CC2
I
CC
I
SB1
I
SB2
I
IL
I
OL
V
IL1
(1)
V
IH1
(1)
V
OL1
V
OH1
Note:
Parameter
Supply Voltage
Supply Voltage
Supply Current
Standby Current
Standby Current
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
V
CC
= 5.0V
V
CC
= 2.7V
V
CC
= 5.0V
V
IN
= 0V to V
CC
V
IN
= 0V to V
CC
2.7V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
I
OL
= 2.1 mA
I
OH
= –0.4 mA
2.4
−−−−0.6
2.0
READ at 1.0 MHz
WRITE at 1.0 MHz
CS = 0V
CS = 0V
Test Condition
Min
2.7
4.5
0.5
0.5
6.0
10.0
0.1
0.1
Typ
Max
5.5
5.5
2.0
2.0
10.0
15.0
3.0
3.0
0.8
V
CC
+ 1
0.4
Unit
V
V
mA
mA
µA
µA
µA
µA
V
V
V
V
1. V
IL
min and V
IH
max are reference only and are not tested.
Table 2-4.
AC Characteristics
Applicable over recommended operating range from T
A
= –40°C to +125°C, V
CC
= As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol
f
SK
t
SKH
t
SKL
t
CS
t
CSS
t
DIS
t
CSH
t
DIH
t
PD1
t
PD0
Parameter
SK Clock
Frequency
SK High Time
SK Low Time
Minimum CS
Low Time
CS Setup Time
DI Setup Time
CS Hold Time
DI Hold Time
Output Delay to ‘1’
Output Delay to ‘0’
Test Condition
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
Relative to SK
Relative to SK
Relative to SK
Relative to SK
AC Test
AC Test
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
Min
0
0
250
250
250
250
250
250
50
50
100
100
0
100
100
250
500
250
500
Typ
Max
2
1
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
5096E–SEEPR–1/08
Table 2-4.
AC Characteristics (Continued)
Applicable over recommended operating range from T
A
= –40°C to +125°C, V
CC
= As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol
t
SV
t
DF
t
WP
Endurance
(1)
Parameter
CS to Status Valid
CS to DO in High
Impedance
Write Cycle Time
5.0V, 25°C
Test Condition
AC Test
AC Test
CS = V
IL
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
0.1
1M
4
Min
Typ
Max
250
250
100
150
10
Units
ns
ns
ms
Write Cycles
Note:
1. This parameter is characterized and is not 100% tested.
Table 2-5.
Instruction
READ
EWEN
ERASE
WRITE
ERAL
WRAL
Instruction Set for the AT93C86A
Address
SB
1
1
1
1
1
1
Op Code
10
00
11
01
00
00
x8
A
10
– A
0
11XXXXXXXXX
A
10
– A
0
A
10
– A
0
10XXXXXXXXX
01XXXXXXXXX
x 16
A
9
– A
0
11XXXXXXXX
A
9
– A
0
A
9
– A
0
10XXXXXXXX
01XXXXXXXX
D
7
– D
0
D
15
– D
0
D
7
– D
0
D
15
– D
0
x8
Data
x 16
Comments
Reads data stored in memory,
at specified address.
Write enable must precede all
programming modes.
Erases memory location A
n
– A
0
.
Writes memory location A
n
– A
0
.
Erases all memory locations.
Valid only at V
CC
= 4.5V to 5.5V.
Writes all memory locations.
Valid when V
CC
= 4.5V to 5.5V and
Disable Register cleared.
Disables all programming
instructions.
EWDS
1
00
00XXXXXXXXX
00XXXXXXXX
4
AT93C86A
5096E–SEEPR–1/08
AT93C86A
3. Functional Description
The AT93C86A is accessed via a simple and versatile 3-wire serial communication interface.
Device operation is controlled by seven instructions issued by the host processor.
A valid
instruction starts with a rising edge of CS
and consists of a Start Bit (logic “1”) followed by the
appropriate Op Code and the desired memory address location.
READ (READ):
The Read (READ) instruction contains the address code for the memory loca-
tion to be read. After the instruction and address are decoded, data from the selected memory
location is available at the serial output pin DO. Output data changes are synchronized with the
rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 8- or
16-bit data output string. The AT93C86A supports sequential read operations. The device will
automatically increment the internal address pointer and clock out the next memory location as
long as CS is held high. In this case, the dummy bit (logic “0”) will not be clocked out between
memory locations, thus allowing for a continuous stream of data to be read.
ERASE/WRITE (EWEN):
To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN)
instruction must be executed first before any programming instructions can be carried out.
Please note that once in the EWEN state, programming remains enabled until an EWDS instruc-
tion is executed or V
CC
power is removed from the part.
ERASE (ERASE):
The Erase (ERASE) instruction programs all bits in the specified memory
location to the logical “1” state. The self-timed erase cycle starts once the Erase instruction and
address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is brought
high after being kept low for a minimum of 250 ns (t
CS
). A logic “1” at pin DO indicates that the
selected memory location has been erased, and the part is ready for another instruction.
WRITE (WRITE):
The Write (WRITE) instruction contains the 8 or 16 bits of data to be written
into the specified memory location. The self-timed programming cycle t
WP
starts after the last bit
of data is received at serial data input pin DI. The DO pin outputs the Ready/Busy status of the
part if CS is brought high after being kept low for a minimum of 250 ns (t
CS
). A logic “0” at DO
indicates that programming is still in progress. A logic “1” indicates that the memory location at
the specified address has been written with the data pattern contained in the instruction and the
part is ready for further instructions.
A Ready/Busy status cannot be obtained if the CS is
brought high after the end of the self-timed programming cycle t
WP
.
ERASE ALL (ERAL):
The Erase All (ERAL) instruction programs every bit in the memory array
to the logic “1” state and is primarily used for testing purposes. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns
(t
CS
). The Eral instruction is valid only at V
CC
= 5.0V
±
10%.
WRITE ALL (WRAL):
The Write All (WRAL) instruction programs all memory locations with the
data patterns specified in the instruction. The DO pin outputs the Ready/Busy status of the part if
CS is brought high after being kept low for a minimum of 250 ns (t
CS
). The Wral instruction is
valid only at V
CC
= 5.0V ± 10%.
ERASE/WRITE DISABLE (EWDS):
To protect against accidental data disturbance, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be exe-
cuted after all programming operations. The operation of the Read instruction is independent of
both the Ewen and Ewds instructions and can be executed at any time.
5
5096E–SEEPR–1/08
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