EEWORLDEEWORLDEEWORLD

Part Number

Search

FP20214151351AHADW

Description
Array/Network Resistor, Center Tap, Thin Film, 1350ohm, 0.05% +/-Tol, -10,10ppm/Cel, 3825,
CategoryPassive components    The resistor   
File Size202KB,3 Pages
ManufacturerVishay
Websitehttp://www.vishay.com
Environmental Compliance
Download Datasheet Parametric View All

FP20214151351AHADW Overview

Array/Network Resistor, Center Tap, Thin Film, 1350ohm, 0.05% +/-Tol, -10,10ppm/Cel, 3825,

FP20214151351AHADW Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid975267596
Reach Compliance Codecompliant
Country Of OriginUSA
ECCN codeEAR99
YTEOL7.2
structureFlatpack
JESD-609 codee3
Network TypeCenter Tap
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package height2.435 mm
Package length9.6 mm
Package formSMT
Package width6.475 mm
method of packingWaffle Pack
resistance1350 Ω
Resistor typeARRAY/NETWORK RESISTOR
seriesFP202
size code3825
technologyTHIN FILM
Temperature Coefficient10 ppm/°C
Terminal surfaceMatte Tin (Sn)
Tolerance0.05%
FP 200, 201, 202
Vishay Thin Film
SURFACE MOUNT
NETWORKS
Hermetic Flat-Pak Resistor Networks
FEATURES
Lead (Pb)-free available
Military/Aerospace
Hermetically sealed
Product may not
be
to scale
Pb-free
Available
RoHS*
COMPLIANT
Vishay Thin Film offers a broad line of precision resistor
networks in hermetic Flat-Packs for surface mount
requirements in military, space or other harsh environmental
applications. These networks provide the long-term stability
necessary to insure continuous specification and
performance over the 20 to 30 year life required for space
applications. The fabrication of these devices is performed
under tight procedural and environmental controls to insure
conformance to all 883C Level H or K requirements. Custom
configurations, values and tolerance combinations are
available with fast turnaround.
PRODUCT CAPABILITIES
Material
Resistance Range
Absolute Resistance Tolerance
Resistance Ratio Tolerance
Absolute TCR
Ratio TCR
Absolute Resistor Stability
Ratio Resistor Stability
Package Power Dissipation
Operating Temperature Range
Passivated nichrome
10
Ω
to 1 MΩ total
1 % to 0.05 %
0.1 % to 0.01 %
± 10, 25, 50 ppm/°C
± 5 ppm/°C standard
1000 ppm/2000 h at 70 °C
300 ppm/2000 h at 70 °C
800 mW/70 °C
- 55 °C to + 125 °C
STANDARD CONFIGURATIONS
FP200
Number of Resistors
Number of Leads
1
7, 8
14, 16
Isolated
500
Ω
- 100 kΩ
FP201
Type Connection
Values Available
Number of Resistors
Number of Leads
Type Connection
1
12, 14
14, 16
Series
500
Ω
- 100 kΩ
FP202
Values Available
Number of Resistors
Number of Leads
Type Connection
Values Available
1
13, 15
14, 16
Common
500
Ω
- 100 kΩ
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 61073
Revision: 05-Mar-08
For technical questions, contact: thin-film@vishay.com
www.vishay.com
45

Recommended Resources

TMS320DM8168/TMS320DM8148/TMS320DM8127/TMS320DM6437DM3730 Development Board
Based on TI Da Vinci series TMS320DM8168 floating-point DSP C674x + ARM Cortex-A8 high-performance video processorPowerful video encoding and decoding capabilities, with 3 independent programmable HD ...
fish001 DSP and ARM Processors
[Flower carving DIY] Interesting and fun music visualization series of small projects (10) --- WS2812 hard board screen
I had the urge to do a series of topics on sound visualization. This topic is a bit difficult and covers a wide range of areas. The related FFT and FHT algorithms are also quite complicated, but I sti...
eagler8 DIY/Open Source Hardware
Playing with Zynq Serial 51——[ex70] RGB2YUV, image enhancement, YUV2RGB IP simulation example
[i=s] This post was last edited by ove learning makes me happy on 2020-3-4 08:35[/i]1. Introduction to Image Enhancement IP The Image Enhancement IP integrated inXilinx 's Vivado can effectively reduc...
ove学习使我快乐 FPGA/CPLD
TI DaVinci Technology
What is Da Vinci Technology?TI's official website has a detailed introduction to Da Vinci technology. Da Vinci technology is not only a DSP+ARM dual-core architecture SOC chip, it also includes a comp...
Aguilera DSP and ARM Processors
A list of classic books on communication principles and an analysis of the characteristics of each book
A list of classic books on communication principles and an analysis of the characteristics of each bookThe beauty of communication tension   Organically combined with Matlab, the author is a front-lin...
ohahaha RF/Wirelessly
FPGA Design Tips
...
至芯科技FPGA大牛 FPGA/CPLD

Popular Articles

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号