K7I163684B
K7I161884B
K7I160884B
Document Title
Advance
512Kx36 & 1Mx18 & 2Mx8 DDRII CIO b4 SRAM
512Kx36-bit, 1Mx18-bit, 2Mx8-bit DDRII CIO b4 SRAM
Revision History
Rev. No.
0.0
History
1. Initial document.
Draft Date
Dec. 16, 2002
Remark
Advance
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Dec. 2002
Rev 0.0
K7I163684B
K7I161884B
K7I160884B
Advance
512Kx36 & 1Mx18 & 2Mx8 DDRII CIO b4 SRAM
512Kx36-bit, 1Mx18-bit, 2Mx8-bit DDRII CIO b4 SRAM
FEATURES
• 1.8V+0.1V/-0.1V Power Supply.
• DLL circuitry for wide output data valid window and future
freguency scaling.
• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,
1.8V+0.1V/-0.1V for 1.8V I/O.
• Pipelined, double-data rate operation.
• Common data input/output bus .
• HSTL I/O
• Full data coherency, providing most current data.
• Synchronous pipeline read with self timed late write.
• Registered address, control and data input/output.
• DDR(Double Data Rate) Interface on read and write ports.
• Fixed 4-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
• Two input clocks(K and K) for accurate DDR timing at clock
rising edges only.
• Two input clocks for output data(C and C) to minimize
clock-skew and flight-time mismatches.
• Two echo clocks (CQ and CQ) to enhance output data
traceability.
• Single address bus.
• Byte write (x18, x36) and nybble(x8) write function.
• Simple depth expansion with no data contention.
• Programmable output impedance.
• JTAG 1149.1 compatible test access port.
• 165FBGA(11x15 ball aray FBGA) with body size of 13x15mm
Organization
Part
Number
K7I163684B-FC33
X36
K7I163684B-FC30
K7I163684B-FC20
K7I163684B-FC16
K7I163684B-FC33
X18
K7I163684B-FC30
K7I163684B-FC20
K7I163684B-FC16
K7I163684B-FC33
X8
K7I163684B-FC30
K7I163684B-FC20
K7I163684B-FC16
Cycle
Time
3.0
3.3
5.0
6.0
3.0
3.3
5.0
6.0
3.0
3.3
5.0
6.0
Access
Time
0.45
0.45
0.45
0.50
0.45
0.45
0.45
0.50
0.45
0.45
0.45
0.50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FUNCTIONAL BLOCK DIAGRAM
36 (or 18)
DATA
REG
36 (or 18)
WRITE DRIVER
WRITE/READ DECODE
OUTPUT SELECT
LD
R /W
BW
X
4(or 2)
CTRL
LOGIC
512kx36
(1Mx18)
MEMORY
ARRAY
72
(or 36)
72
(or 36)
OUTPUT DRIVER
ADDRESS
A0,A1
SENSE AMPS
OUTPUT REG
17 (or 18)
ADD REG
&
BURST
LOGIC
17
(or 18)
36 (or 18)
DQ
CQ, CQ
(Echo Clock out)
K
K
C
C
CLK
GEN
SELECT OUTPUT CONTROL
Notes:
1. Numbers in ( ) are for x18 device, x8 device also the same with appropriate adjustments of depth and width.
DDRII SRAM and Double Data Rate comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and Samsung te chnology.
-2-
Dec. 2002
Rev 0.0
K7I163684B
K7I161884B
K7I160884B
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
V
SS/
SA*
DQ27
NC
DQ29
NC
DQ30
DQ31
V
REF
NC
NC
DQ33
NC
DQ35
NC
TCK
3
NC/SA*
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
V
DDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
SA
Advance
512Kx36 & 1Mx18 & 2Mx8 DDRII CIO b4 SRAM
4
R /W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
B W
2
B W
3
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
SA0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
BW
1
BW
0
SA1
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
V
SS/
SA*
NC
DQ17
NC
DQ15
NC
NC
V
REF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
PIN CONFIGURATIONS
(TOP VIEW)
K7I163684B(512Kx36)
Notes :
1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 3A for 32Mb, 10A for 64Mb, 2A for 128Mb .
2. BW
0
controls write to DQ0:DQ8, BW
1
controls write to DQ9:DQ17, BW
2
controls write to DQ18:DQ26 and BW
3
controls write to DQ27:DQ35.
PIN NAME
SYMBOL
K, K
C, C
CQ, CQ
Doff
SA0,SA1
SA
DQ0-35
PIN NUMBERS
6B, 6A
6P, 6R
11A, 1A
1H
6C,7C
9A,4B,8B,5C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
2B,3B,11B,3C,10C,11C,2D,3D,11D,3E,10E,11E,2F,3F
11F,2G,3G,11G,3J,10J,11J,3K,10K,11K,2L,3L,11L
3M,10M,11M,2N,3N,11N,3P,10P,11P
4A
8A
7B,7A,5A,5B
2H,10H
11H
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,
4M-8M,4N,8N
10R
11R
2R
1R
3A,1B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,
1F,9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K
1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P
DESCRIPTION
Input Clock
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Burst Count Address Inputs
Address Inputs
Data Inputs Outputs
Read, Write Control Pin, Read active
when high
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
Block Write Control Pin,active when low
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply ( 1.8 V )
Output Power Supply ( 1.5V or 1.8V )
Ground
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
JTAG Test Data Output
No Connect
3
2
1
NOTE
R/W
LD
B W
0
, BW
1,
BW
2
, B W
3
V
REF
ZQ
V
DD
V
DDQ
V
SS
TMS
TDI
TCK
TDO
NC
Notes:
1. C, C, K or K cannot be set to V
REF
voltage.
2. When ZQ pin is directly connected to V
DD
output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
-3-
Dec. 2002
Rev 0.0
K7I163684B
K7I161884B
K7I160884B
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
V
SS/
SA*
DQ9
NC
NC
NC
DQ12
NC
V
REF
NC
NC
DQ15
NC
NC
NC
TCK
3
SA
NC
NC
DQ10
DQ11
NC
DQ13
V
DDQ
NC
DQ14
NC
NC
DQ16
DQ17
SA
Advance
512Kx36 & 1Mx18 & 2Mx8 DDRII CIO b4 SRAM
4
R/ W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW
1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
SA0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
NC
BW
0
SA1
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
Vss/SA*
NC
DQ7
NC
NC
NC
NC
V
REF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
PIN CONFIGURATIONS
(TOP VIEW)
K7I161884B(1Mx18)
Notes:
1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 10A for 32Mb, 2A for 64Mb.
2. BW
0
controls write to DQ0:DQ8 and BW
1
controls write to DQ9:DQ17.
PIN NAME
SYMBOL
K, K
C, C
CQ, C Q
Doff
SA0,SA1
SA
DQ0-17
R/ W
LD
B W
0
, BW
1
V
REF
ZQ
V
DD
V
DDQ
V
SS
TMS
TDI
TCK
TDO
PIN NUMBERS
6B, 6A
6P, 6R
11A, 1A
1H
6C,7C
3A,9A,4B,8B,5C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
2B,11B,10C,3D,3E,11E,2F,11F,3G,10J,3K,11K,2L,11L
10M,3N,3P,11P
4A
8A
7B, 5A
2H,10H
11H
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
10A,2A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
10R
11R
2R
1R
7A,1B,3B,5B,9B,10B,1C,2C,3C,9C,11C,1D,2D,9D,10D,11D
1E,2E,9E,10E,1F,3F,9F,10F,1G,2G,9G,10G,11G
1J,2J,3J,9J,11J,1K,2K,9K,10K,1L,3L,9L,10L
1M,2M,3M,9M,11M,1N,2N,9N,10N,11N,1P,2P,9P,10P
DESCRIPTION
Input Clock
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Burst Count Address Inputs
Address Inputs
Data Inputs Outputs
Read, Write Control Pin, Read active
when high
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
Block Write Control Pin,active when low
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply ( 1.8 V )
Output Power Supply ( 1.5V or 1.8V )
Ground
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
JTAG Test Data Output
2
1
NOTE
NC
No Connect
3
Notes:
1. C, C, K or K cannot be set to V
R E F
voltage.
2. When ZQ pin is directly connected to V
D D
output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
-4-
Dec. 2002
Rev 0.0
K7I163684B
K7I161884B
K7I160884B
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
V
SS/
SA*
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ6
NC
NC
NC
TCK
3
SA
NC
NC
NC
DQ4
NC
DQ5
V
DDQ
NC
NC
NC
NC
NC
DQ7
SA
Advance
512Kx36 & 1Mx18 & 2Mx8 DDRII CIO b4 SRAM
4
R/ W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
NW
1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
NC
NW
0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
Vss/SA*
NC
NC
NC
NC
NC
NC
V
REF
DQ1
NC
NC
NC
NC
NC
TMS
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
NC
NC
DQ0
NC
NC
NC
TDI
PIN CONFIGURATIONS
(TOP VIEW)
K7I160884B(2Mx8)
Notes:
1. * Checked No Connect(NC) pin is reserved for higher density address, i.e. 2A for 72Mb.
2. NW
0
controls write to DQ0:DQ3 and NW
1
controls write to DQ4:DQ7.
PIN NAME
SYMBOL
K, K
C, C
CQ, C Q
Doff
SA
DQ0-7
R/ W
LD
NW
0
, NW
1
V
REF
ZQ
V
DD
V
DDQ
V
SS
TMS
TDI
TCK
TDO
PIN NUMBERS
6B, 6A
6P, 6R
11A, 1A
1H
3A,9A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
10J,11B,3E,11E,3G,2L,11L,3P
4A
8A
7B, 5A
2H,10H
11H
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
10R
11R
2R
1R
7A,1B,2B,3B,5B,9B,10B,1C,2C,3C,7C,9C,10C,11C
1D,2D,3D,9D,10D,11D,1E,2E,9E,10E,1F,2F,3F,9F,10F,11F
1G,2G,9G,10G,11G,1J,2J,3J,9J,11J,1K,2K,3K,9K,10K,11K
1L,3L,9L,10L,1M,2M,3M,9M,10M,11M,1N,2N,3N,9N,10N
11N,1P,2P,9P,10P,11P
DESCRIPTION
Input Clock
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Address Inputs
Data Inputs Outputs
Read, Write Control Pin, Read active
when high
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
Nybble Write Control Pin,active when low
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply ( 1.8 V )
Output Power Supply ( 1.5V or 1.8V )
Ground
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
JTAG Test Data Output
2
1
NOTE
NC
No Connect
3
Notes:
1. C, C, K or K cannot be set to V
R E F
voltage.
2. When ZQ pin is directly connected to V
D D
output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
4. The X8 product does not permit random start address on the least significant address bit.
-5-
Dec. 2002
Rev 0.0
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