[i=s]This post was last edited by wsmysyn on 2018-7-29 10:09[/i] As the title: I was debugging FPGA recently and needed to burn the code into Flash; but the jic file was downloaded successfully but th...
Headhunting position [Chengdu] Job responsibilities: 1. According to the company's business requirements, develop embedded software for R&D products and test platforms; 2. Responsible for the design, ...
The SCLK output was not adjusted overnight.
The Verilog program has been written. The SCLK output is normal during simulation, but ILA does not know why SCLK always has no output. There was a version ...
[i=s] This post was last edited by shihuntaotie on 2019-1-9 21:39 [/i] [font=宋体][size=4] Read all sensor data of the kit according to the evaluation plan, and still use the online IDE for programming....